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SL11R
SL11R USB Controller/ 16-Bit RISC Processor Data Sheet
Cypress Semiconductor Corporation Document #: 38-08006 Rev. **
*
3901 North First Street
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San Jose
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CA 95134 * 408-943-2600 Revised December 3, 2001
SL11R
Table of Contents 1.0 DEFINITIONS .................................................................................................................................. 8 2.0 REFERENCES ................................................................................................................................ 8 3.0 INTRODUCTION ............................................................................................................................. 8
3.1 Overview ......................................................................................................................................... 8 3.2 SL11R Features .............................................................................................................................. 8 3.3 SL11R 16-Bit RISC Processor .................................................................................................... 10 3.4 3Kx16 Mask ROM and BIOS ........................................................................................................ 10 3.5 Internal RAM ................................................................................................................................. 10 3.6 Clock Generator ........................................................................................................................... 11 3.7 USB Interface ............................................................................................................................... 11 3.8 Processor Control Registers ...................................................................................................... 11 3.9 Interrupts ...................................................................................................................................... 11 3.10 UART Interface ........................................................................................................................... 11 3.11 *2-wire Serial EEPROM Interface .............................................................................................. 11 3.12 External SRAM/DRAM/EPROM Interface ................................................................................. 11 3.13 General Timers and Watch Dog Timer ..................................................................................... 11 3.14 Special GPIO Functionality for Suspend, Resume and Low Power modes ......................... 11 3.15 Programmable Pulse/PWM Interface ....................................................................................... 11 3.16 Mailbox and DMA Overview ...................................................................................................... 12 3.17 Mailbox Interface ....................................................................................................................... 12 3.18 DMA Interface ............................................................................................................................. 13 3.19 Fast DMA Mode .......................................................................................................................... 14 3.20 SL11R Interface Modes ............................................................................................................. 14
3.20.1 3.20.2 3.20.3 3.20.4 General Purpose IO mode (GPIO) ................................................................................................... 15 8/16-bit DMA Mode ........................................................................................................................... 15 Fast EPP Mode .................................................................................................................................. 15 DVC 8-bit DMA Mode ........................................................................................................................15
4.0 INTERFACE .................................................................................................................................. 15
4.1 4.2 4.3 4.4 4.5
Internal Masked ROM: 0xE800-0xFFFF ...................................................................................... 15 External ROM: 0xC100-0xE800 ................................................................................................... 15 Internal RAM: 0x0000-0x0BFF .................................................................................................... 16 Clock Generator ........................................................................................................................... 16 USB Interface ............................................................................................................................... 18
4.5.1 4.5.2 4.5.3 4.5.4 USB Global Control & Status Register (0xC080: R/W) ....................................................................18 USB Frame Number Register (0xC082: Read Only) ........................................................................ 18 USB Address Register (0xC084: R/W) ..............................................................................................18 USB Command Done Register (0xC086: Write Only) ...................................................................... 19
4.6 4.7 4.8 4.9
USB Endpoint 0 Control & Status Register (0xC090: R/W) USB Endpoint 1 Control & Status Register (0xC092: R/W) USB Endpoint 2 Control & Status Register (0xC094: R/W) USB Endpoint 3 Control & Status Register (0xC096: R/W)
4.9.1 4.9.2 4.9.3 4.9.4 4.9.5 4.9.6 4.9.7
...................................................... 19 ...................................................... 19 ...................................................... 19 ...................................................... 19
General Description for All Endpoints from Endpoint 0 to Endpoint 3 ......................................... 19 USB Endpoints Control (For Writing) ............................................................................................... 19 USB Endpoints Status (For Reading) ............................................................................................... 20 USB Endpoint 0 Address Register (0x0120: R/W) ........................................................................... 20 USB Endpoint 1 Address Register (0x0124: R/W) ........................................................................... 20 USB Endpoint 2 Address Register (0x0128: R/W) ........................................................................... 20 USB Endpoint 3 Address Register (0x012C: R/W) ..........................................................................20
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SL11R
Table of Contents (continued)
4.9.8 USB Endpoint 0 Count Register (0x0122: R/W) ............................................................................... 20 4.9.9 USB Endpoint 1 Count Register (0x0126: R/W) ............................................................................... 20 4.9.10 USB Endpoint 2 Count Register (0x012A: R/W) ............................................................................ 20 4.9.11 USB Endpoint 3 Count Register (0x012E: R/W) ............................................................................. 21
4.10 Processor Control Registers .................................................................................................... 21
4.10.1 4.10.2 4.10.3 4.10.4 4.11.1 4.11.2 4.11.3 4.11.4 4.12.1 4.12.2 4.12.3 4.12.4 Configuration Register (0xC006: R/W) ........................................................................................... 21 Speed Control Register (0xC008: R/W) .......................................................................................... 22 Power Down Control Register (0xC00A: R/W) ............................................................................... 23 Breakpoint Register (0xC014: R/W) ................................................................................................ 23 Hardware Interrupts ......................................................................................................................... 24 Interrupt Enable Register (0xC00E: R/W) .......................................................................................24 GPIO Interrupt Control Register (0xC01C: R/W) ............................................................................ 25 Software Interrupts ........................................................................................................................... 25 UART Control Register (0xC0E0: R/W) ........................................................................................... 27 UART Status Register (0xC0E2: Read Only) .................................................................................. 28 UART Transmit Data Register (0xC0E4: Write Only) ..................................................................... 28 UART Receive Data Register (0xC0E4: Read Only) ...................................................................... 28
4.11 Interrupts .................................................................................................................................... 23
4.12 UART Interface. .......................................................................................................................... 27
4.13 Serial EEPROM Interface (2-wire serial interface) .................................................................. 28 4.14 External SRAM, EPROM, DRAM ............................................................................................... 29
4.14.1 4.14.2 4.14.3 4.14.4 4.14.5 4.14.6 Memory Control Register (0xC03E: R/W) .......................................................................................30 Extended Memory Control Register (0xC03A: R/W) ...................................................................... 30 Extended Page 1 Map Register (0xC018: R/W) .............................................................................. 30 Extended Page 2 Map Register (0xC01A: R/W) ............................................................................. 31 DRAM Control Register (0xC038: R/W) .......................................................................................... 31 Memory Map ...................................................................................................................................... 31
4.15 General Timers and Watch Dog Timer ..................................................................................... 33
4.15.1 Timer 0 Count Register (0xC010: R/W) ........................................................................................... 33 4.15.2 Timer 1 Count Register (0xC012: R/W) ........................................................................................... 33 4.15.3 Watchdog Timer Count & Control Register (0xC00C: R/W) ......................................................... 33
4.16 Special GPIO Function for Suspend, Resume and Low-Power modes ................................ 33 4.17 Programmable Pulse/PWM Interface ....................................................................................... 34
4.17.1 PWM Control Register (0xC0E6: R/W) ............................................................................................ 34 4.17.2 PWM Maximum Count Register (0xC0E8: R/W) ............................................................................. 35 4.17.3 PWM Channel 0 Start Register (0xC0EA: R/W) .............................................................................. 35 4.17.4 PWM Channel 0 Stop Register (0xC0EC: R/W) .............................................................................. 36 4.17.5 PWM Channel 1 Start Register (0xC0EE: R/W) .............................................................................. 36 4.17.6 PWM Channel 1 Stop Register (0xC0F0: R/W) ............................................................................... 36 4.17.7 PWM Channel 2 Start Register (0xC0F2: R/W) ............................................................................... 36 4.17.8 PWM Channel 2 Stop Register (0xC0F4: R/W) ............................................................................... 36 4.17.9 PWM Channel 3 Start Register (0xC0F6: R/W) ............................................................................... 36 4.17.10 PWM Channel 3 Stop Register (0xC0F8: R/W) ............................................................................. 37 4.17.11 PWM Cycle Count Register (0xC0FA: R/W) .................................................................................37
4.18 Fast DMA Mode .......................................................................................................................... 37
4.18.1 4.18.2 4.18.3 4.18.4 4.18.5 DMA Control Register (0xC02A: R/W) ............................................................................................ 37 Low DMA Start Address Register (0xC02C: R/W) ......................................................................... 37 High DMA Start Address Register (0xC02E: R/W) ......................................................................... 38 Low DMA Stop Address Register (0xC030: R/W) ..........................................................................38 High DMA Stop Address Register (0xC032: R/W) ......................................................................... 38
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SL11R
Table of Contents (continued) 5.0 SL11R INTERFACE MODES ........................................................................................................ 38
5.1 General Purpose IO mode (GPIO) .............................................................................................. 38
5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 5.1.6 5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.2.6 5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 5.3.6 5.3.7 I/O Control Register 0 (0xC022: R/W) ............................................................................................... 39 I/O Control Register 1 (0xC028: R/W) ............................................................................................... 39 Output Data Register 0 (0xC01E: R/W) ............................................................................................. 39 Output Data Register 1 (0xC024: R/W) ............................................................................................. 39 Input Data Register 0 (0xC020: Read only) ...................................................................................... 39 Input Data Register 1 (0xC026: Read only) ...................................................................................... 39 Mailbox Protocol ................................................................................................................................. 41 INBUFF Data Register (0xC0C4: R/W) ..............................................................................................41 OUTBUFF Data Register (0xC0C4: R/W) .......................................................................................... 41 STATUS Register (0xC0C2: Read Only) ........................................................................................... 42 DMA Protocol ...................................................................................................................................... 42 DMA Control Register (0xC0C0: R/W) ..............................................................................................42 EPP Data Register (0xC040: R/W) ..................................................................................................... 43 EPP Address Register (0xC044: R/W) ..............................................................................................43 EPP Address Buffer Read Register (0xC046: Read Only) .............................................................. 43 EPP Data Buffer Read Register (0xC042: Read Only) ..................................................................... 43 EPP Status Data Register (0xC04E: R/W) ......................................................................................... 43 EPP P_REG Register (0xC050: R/W) ................................................................................................. 44 Serial Interface Registers .................................................................................................................. 44
Serial Interface Control & Status Register ............................................................................................... Serial Interface Address Register .............................................................................................................. Serial Interface Data Write Register........................................................................................................... Serial Interface Data Read Register .......................................................................................................... 44 44 44 45
5.2 8/16-bit DMA Mode ....................................................................................................................... 40
5.3 Fast EPP Mode ............................................................................................................................. 42
5.3.7.1 5.3.7.2 5.3.7.3 5.3.7.4
5.4 DVC 8-bit DMA Mode ................................................................................................................... 45
5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 5.4.6 5.4.7 Video Status Register ......................................................................................................................... 45 Camera Serial Interface Registers ....................................................................................................46 Serial Interface Control & Status Register (0xC068: R/W) .............................................................. 46 Serial Interface Address Register (0xC06A: Write Only) ................................................................ 46 Serial Interface Data Write Register (0xC06C: Write Only) ............................................................. 46 Serial Interface Data Read Register (0xC06C: Read Only) ............................................................. 47 I/O Address Map ................................................................................................................................. 47
6.0 PHYSICAL CONNECTION ........................................................................................................... 49
6.1 6.2 6.3 6.4 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8
Package Type ............................................................................................................................... 49 GPIO and 8/16-Bit DMA Modes--Pin Assignment and Description ........................................ 49 Fast EPP Pin Assignment and Description ............................................................................... 52 DVC 8-Bit DMA Mode Pin Assignment and Description .......................................................... 54 Instruction Set Overview ............................................................................................................. 57 Reset Vector ................................................................................................................................. 57 Register Set .................................................................................................................................. 57 General-Purpose Registers ........................................................................................................ 57 General Purpose/Address Registers ......................................................................................... 58 REGBANK Register (0xC002: R/W) ............................................................................................ 58 Flags Register (0xC000: Read Only) .......................................................................................... 58 Instruction Format ....................................................................................................................... 58
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7.0 SL11R CPU PROGRAMMING GUIDE ......................................................................................... 57
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SL11R
Table of Contents (continued)
7.9 Addressing Modes ....................................................................................................................... 59 7.10 Register Addressing .................................................................................................................. 59 7.11 Immediate Addressing .............................................................................................................. 59 7.12 Direct Addressing ...................................................................................................................... 59 7.13 Indirect Addressing ................................................................................................................... 59 7.14 Indirect Addressing with Auto Increment ............................................................................... 60 7.15 Indirect Addressing with Offset ............................................................................................... 60 7.16 Stack Pointer (R15) Special Handling ...................................................................................... 60 7.17 Dual Operand Instructions ........................................................................................................ 60 7.18 Program Control Instructions ................................................................................................... 62 7.19 Single Operand Operation Instructions ................................................................................... 63 7.20 Miscellaneous Instructions ....................................................................................................... 65 7.21 Built-in Macros ........................................................................................................................... 65 7.22 SL11R Processor Instruction Set Summary ........................................................................... 66
8.0 SL11R - ELECTRICAL SPECIFICATION ..................................................................................... 67
8.1 Absolute Maximum Ratings ........................................................................................................ 67 8.2 Recommended Operating Conditions ....................................................................................... 67 8.3 Crystal Requirements (XTAL1, XTAL2) ..................................................................................... 68 8.4 External Clock Input Characteristics (XTAL1) .......................................................................... 68 8.5 SL11R DC Characteristics .......................................................................................................... 68 8.6 SL11R USB Transceiver Characteristics ................................................................................... 69 8.7 SL11R Reset Timing .................................................................................................................... 69 8.8 SL11R Clock Timing Specifications ........................................................................................... 69 8.9 8/16-bit DMA & DVC 8-bit DMA Mode: SDATA Port I/O Read Cycle (Non-DMA) .................... 70 8.10 8/16-bit DMA & DVC 8-bit DMA Mode: SDATA Port I/O Write Cycle (Non-DMA) .................. 71 8.11 8/16-bit DMA & DVC 8-bit DMA Mode: SDATA, DMA Read Cycle ........................................ 72 8.12 8/16-bit DMA & DVC 8-bit DMA Mode: SDATA, DMA Write Cycle ......................................... 72 8.13 SL11R Signals Name convention ............................................................................................. 72 8.14 SL11R DRAM Timing ................................................................................................................. 73 8.15 SL11R DRAM Read Cycle ........................................................................................................ 74 8.16 SL11R DRAM Write Cycle ........................................................................................................ 75 8.17 SL11R CAS-Before-RAS Refresh Cycle ................................................................................... 76 8.18 SL11R DRAM Page Mode Read Cycle ..................................................................................... 77 8.19 DRAM Page Mode Write Cycle ................................................................................................. 78 8.20 SL11R SRAM Read Cycle .......................................................................................................... 79 8.21 SL11R SRAM Write Cycle ......................................................................................................... 80 8.22 2-Wire Serial Interface EEPROM Timing .................................................................................. 81 8.23 Fast EPP Data/Address Read Cycle ......................................................................................... 82 8.24 Fast EPP Data/Address Write Cycle ........................................................................................ 82
9.0 PACKAGE INFORMATION .......................................................................................................... 83
9.1 Drawings and Dimensions .......................................................................................................... 83 9.2 Package Markings ....................................................................................................................... 84 9.3 Thermal Specifications ............................................................................................................... 84
10.0 REVISION HISTORY ................................................................................................................... 85
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SL11R
List of Figures
Figure 3-1. SL11R Block Diagram .................................................................................................... 10 Figure 3-2. Functional Logic Diagram .............................................................................................. 12 Figure 3-3. Mailbox/DMA Read ......................................................................................................... 13 Figure 3-4. Mailbox/DMA Write ......................................................................................................... 14 Figure 4-1. 48-MHz Crystal Circuit ................................................................................................... 17 Figure 4-2. 12-MHz Crystal Circuit ................................................................................................... 17 Figure 4-3. UART Port Connection ................................................................................................... 27 Figure 4-4. 2-Wire Serial Interface 2K-byte Connection ................................................................. 29 Figure 4-5. 2-Wire Serial Interface 16K Connection ....................................................................... 29 Figure 4-6. Special GPIO Pull-up Connection Example ................................................................. 34 Figure 4-7. PWM Block Diagram ....................................................................................................... 34 Figure 5-1. GPIO Mode Block Diagram\ ........................................................................................... 40 Figure 5-2. 8/16-bit DMA Mode Block Diagram ............................................................................... 41
List of Tables Table 4-1. Table 4-2. Table 4-3. Table 4-4. Table 4-5. Internal Masked ROM (SL11R BIOS) .............................................................................. 15 Internal RAM Memory Usage .......................................................................................... 16 Hardware Interrupt Table ................................................................................................. 24 Software Interrupt Table .................................................................................................. 26 Memory Map ..................................................................................................................... 32
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SL11R
License Agreement
Use of this document and the intellectual properties contained herein indicates acceptance of the following License Agreement. If you do not accept the terms of this License Agreement, do not use this document, nor the associated intellectual properties, nor any other material you received in association with this product, and return this document and the associated materials within fifteen (15) days to Cypress Semiconductor Corporation or (CY) or CY's authorized distributor from whom you purchased the product. 1. You can only legally obtain CY's intellectual properties contained in this document through CY or its authorized distributors. 2. You are granted a nontransferable license to use and to incorporate CY's intellectual properties contained in this document into your product. The product may be either for your own use or for sale. 3. You may not reverse-engineer the SL11R or otherwise attempt to discover the designs of SL11R. 4. You may not assign, distribute, sell, transfer, or disclose CY's intellectual properties contained in this document to any other person or entity. 5. This license terminates if you fail to comply with any of the provisions of this Agreement. You agree upon termination to destroy this document, stop using the intellectual properties contained in this document and any of its modification and incorporated or merged portions in any form, and destroy any unused SL11R chips.
Warranty Disclaimer and Limited Liability
Cypress Semiconductor Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Cypress's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Cypress are granted by the Company in connection with the sale of Cypress products, expressly or by implication. Cypress's products are not authorized for use as critical components in life support devices or systems. SL11R is a trademark of the Cypress Semiconductor Corporation. All other product names are trademarks or registered trademarks of their respective owners.
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SL11R
1.0
USB SL11R QT QTS QTU R/W PLL PWM DVC MFU WDT RAM EPP
Definitions
Universal Serial Bus The SL11R is a Cypress USB Controller, which provides multiple functions on a single chip. Quick stream data Transfer engine, which contains a small set of RISC instructions designed for the SL11R USB controller. `QT' is a naming convention that represents QT Engine utility tools. For example: `QTS' indicates all tools, which interface with the RS232 serial interface port. QT Engine Tools that interface with the USB port Read/Write Phase Lock Loop. Pulse Width Modulation Digital Video Camera Multi Function Units Watch Dog Timer Random Access Memory Enhanced Parallel Port: An asynchronous, byte-wide, bidirectional channel controlled by the host device. This mode provides separate address and data cycles over the eight data lines of the interface. SL11R Registers: R0-R7 Data registers or general-purpose registers. R8-R14 Address/Data registers, or general-purpose registers. R15 Stack pointer register. A simulation model similar to 80x86 BIOS
2-wire serial interface 2-wire Serial EEPROM interface. R0-R15
SL11R BIOS
2.0
References
[Ref. 1] SL11R_BIOS [Ref. 2] SL11R_TOOLS [Ref. 3] Universal Serial Bus Specification 1.1
3.0
3.1
Introduction
Overview
The SL11R is a low-cost, high-speed Universal Serial Bus (USB) RISC based Controller. It contains a 16-bit RISC processor with built-in SL11R BIOS ROM to greatly reduce firmware development work. Its 2-wire serial EEPROM interface offers low cost storage for USB device configuration and customer's product-specific functions. New functions can be programmed into the 2-wire serial interface by downloading them from a USB Host PC. This unique architecture provides the ability to upgrade products in the field without changing the peripheral hardware. The SL11R Processor can execute code from either internal ROM/RAM or external ROM and SRAM. The SL11R Programmable bidirectional Data Port supports both DMA and I/O modes. A built in USB port supports data transfers up to 12 MBits/sec which is the maximum USB transfer rate. All USB protocol modes are supported: Isochronous (up to 1024 bytes/packet), Bulk, Interrupt, and Control. The SL11R requires a 3.3-Volt power supply, which can be powered via a USB host PC or a Hub. Suspend/Resume, and Low power modes are available. The SL11R offers an optimal solution for a variety of peripheral products such as: Scanners, Digital Cameras (Video and Still), Color Printers, Multi-function Units (MFU), Faxes, External Storage devices, Monitors, Connectivity boxes, and other peripherals that traditionally interface via EPP or SCSI to a host PC.
3.2
SL11R Features
* Cypress offers a Development Kit for each of its product lines. These Development Kits include multiple peripheral Mini-port class drivers for Windows 98/ME/2000, firmware source code and demo USB source code for a variety of applications. Also available is an SL11R "C" compiler, debugger, and assembler with a reference demo board. * 48 MHz 16 bit RISC Processor * Up to 16 bits of Programmable Bidirectional Data I/O Document #: 38-08006 Rev. ** Page 8 of 85
SL11R
* Up to 32 bits of General Purpose I/O (GPIO) * 6Kx8 internal Mask ROM with built-in BIOS in supporting a comprehensive list of interrupt calls (see [Ref. 1] SL11R_BIOS for detailed information). These include USB functions, 2-wire serial interface, and UART and Boot-Up options (Boot-up from 2-wire serial interface or External ROM). Executable code can also run from 8-bit or 16-bit external Memory. * 3Kx8 internal RAM that can be configured as the USB Ping-Pong buffer for USB DATA0 and DATA1 packets. It also can be used for data and/or code. * Two-wire serial EEPROM interface port with SL11R BIOS support to allow on-board EEPROM programming * Flexible Programmable external memory wait-states and a 8/16 data path * Up to 16-bit address for Extended Memory Interface Port for External SRAM and ROM * On chip DRAM Controller * On chip fast EPP Interface * On chip 8/16-bit DMA data path interface * Supports 12 MHz/48MHz external crystal or clock * Executable code or data can be loaded either from the USB port or via the UART port. The code/data is moved to RAM for debugging purposes (using a break point register), or to be programmed via a two-wire serial EEPROM. * USB Port (12 Mbits/sec), including a built-in USB transceiver. All USB standard protocol modes are supported: Isochronous mode (up to 1024 packet size), Bulk, Interrupt, and Control modes. * There are four available Endpoints. Each endpoint utilizes a bidirectional DMA port to move data between the Memory and the USB. Data can be sent/received to/from the Data Port Independently. * Two General Purpose Timers, a Watchdog timer (WDT), four programmable PWM channels, and four Programmable Timing Generator outputs * Four PWM or Programmable Timing Generator output channels are available. Each channel provides a programmable timing generator sequence that can be used to interface to various CCD, CIS, and CMOS image sensors, or can be used for other types of applications. * Suspend/Resume and Low Power modes are supported * UART interface supports from 900 Baud to 115.2K Baud * USB Generic Mini-Port Driver for WIN98/2000 is available * Debugger and QT-Assembler are available * "C" Compiler option available * Package: 100 LPQFP * Power requirements 3.3V
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SL11R
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3.3
SL11R 16-Bit RISC Processor
The SL11R can be used as a general purpose 16 bit embedded processor. It includes a USB interface (Universal Serial Bus) and up to 32 bits of GPIO supporting a variety of functions and modes. The 16-bit main data port can be used in either I/O or DMA bidirectional modes. Also, the SL11R contains 4 PWM channels or four Programmable Time Generator (PTG) signals, a UART, a 2-wire serial EEPROM interface, an additional External DRAM or SRAM interface for extended memory, two Timers, a Watchdog Timer, an internal mask BIOS ROM (3kx16) and an SRAM (3Kx8). The SL11R is optimized to offer maximum flexibility in the implementation of a variety of applications such as: Embedded Digital Video USB controller, USB Scanner controller, USB Cable Modems, Printers, External Storage Devices, MFU, etc. The SL11R contains a specialized instruction set (RISC) that is highly optimized to provide efficient coding for a variety of applications such as video processing algorithms, Network data packet translation and USB transaction processing. The SL11R includes a simple software interface for all USB transaction processing, which supports Bulk mode (up to 64 Bytes/packet), Isochronous mode (up to 1024 Bytes/packet), all Interrupt and Control modes.
3.4
3Kx16 Mask ROM and BIOS
The SL11R has a built in 3Kx16 Mask ROM that contains the SL11R BIOS. This BIOS ROM provides the software interface for the USB and a boot-up option for a 2-wire serial interface or an external 8/16 EEPROM.
3.5
Internal RAM
The SL11R contains 3K x 8 internal RAM. The RAM can be used for code/program, variables, buffer I/O, DMA data (i.e. Video data), and USB packets. This memory can be accessed by the 16-Bit processor for data manipulation or by the SIE (Serial Interface Engine), which receives or sends USB host data. Document #: 38-08006 Rev. ** Page 10 of 85
SL11R
3.6
Clock Generator
A 12, 48 MHz external Crystal, or logic-level clock can be used with the SL11R. Two pins, X1 and X2, are provided to connect a low cost crystal circuit to the device. If a logic-level clock is available, it may be connected directly to the X1 pin instead of a crystal. Register C006 must be configured appropriately depending on the frequency used.
3.7
USB Interface
The SL11R has a built-in SIE and USB transceiver that meet the USB (Universal Serial Bus) specification v1.1. The transceiver is capable of transmitting or receiving serial data at the USB maximum data rate of 12 Mbits/sec. The SL11R Controller supports four endpoints. Endpoint 0 is the default pipe and is used to initialize and manipulate the peripheral device. It also provides access to the peripheral device's configuration information, and supports control transfers. Endpoint 1,2, and 3 support Interrupt transfers, Bulk transfers (up to 64 Bytes/packet), or Isochronous transfers (up to 1024 Bytes/packet size).
3.8
Processor Control Registers
The SL11R provides software control registers that can be used to configure the chip mode, the clock generator, the software breakpoint, and to read the BIOS version.
3.9
Interrupts
The SL11R provides 127 interrupt vectors for it's BIOS software interface (see [Ref. 1] SL11R_BIOS).
3.10
UART Interface
The SL11R has a built-in UART interface, which supports data rates from 900 baud to 115.2K Baud. It can be used as a development port or for other interface requirements. The Cypress development environment for the SL11R chip includes a debugger and assembler. Optional "C" compiler is also available[1]. You can download modified code to internal SRAM and debug it using the built-in Breakpoint register and Breakpoint Interrupt to break on any specified address location.
3.11
*2-wire Serial EEPROM Interface
The SL11R provides an interface to an external serial EEPROM. The interface is implemented using General Purpose I/O signals. A variety of serial EEPROM formats can be supported; currently the BIOS ROM supports a two-wire serial EEPROM. A serial EEPROM can be used to store specific Peripheral USB configuration and value-added functions. In addition, serial EEPROM can be used for field product upgrades.
3.12
External SRAM/DRAM/EPROM Interface
The SL11R provides a multiplexed address port and an 8/16-bit data port. This port can be configured to interface to an external SRAM, EPROM or DRAM. The port provides nRAS; nCASL, nCASH, nDRAMWR and nDRAMOE control signals for data access and refresh cycles to the DRAM.
3.13
General Timers and Watch Dog Timer
The SL11R has two built in programmable timers that can provide an interrupt to the SL11R Engine. On every clock tick which is 1 microsecond the timers decrement. An interrupt occurs when the timer reaches zero. A separate Watchdog timer is also provided to provide a fail-safe mechanism. The Watchdog timer can also interrupt the SL11R processor.
3.14
Special GPIO Functionality for Suspend, Resume and Low Power modes
The SL11R CPU supports suspend, resume and CPU low power modes. The SL11R BIOS assigns GPIO29 for the USB DATA+ line pull-up (this pin can simulate USB cable removal or insertion while the USB power is still applied to the board) and the GPIO20 for controlling the power off function.
3.15
Programmable Pulse/PWM Interface
The SL11R has four built-in PWM output channels available under 8/16-bit DMA mode. Each channel provides a programmable timing generator sequence that can be used to interface to various lines CCD, CIS, CMOS image sensors or can be used for other various applications. This feature is only available in the 8/16-bit DMA Mode.
Note: 1. Contact Cypress for details. (support@scanlogic.com)
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SL11R
3.16
Mailbox and DMA Overview
The Mailbox and DMA protocol use the same data latching and steering logic, so it is important to note that in a system where both mechanisms are used, the system designer must be careful to ensure that one type of transfer is finished before the next is started. Setting bits 1 and 2 to `1' in register 0xC006 enables the Mailbox/DMA interface. All transfers to and from the Data Registers are made through GPIO 0 to 15. Data written into the SL11R is latched into a 16-bit register on the rising edge of nWR (GPIO 17) when ADDR (GPIO 19) is high and nCS (GPIO 18) is low. Data is read out of the SL11R by asserting nRD (GPIO 16) low while ADDR (GPIO 19) is high and nCS (GPIO 18) is low. This also applies when data is written or read during DMA transfers. A functional logic diagram is shown in Figure 3-2.
(1 of 16)
SD15-0
D
Q
Internal Data Bus
ADDR/GPIO19 nCS/GPIO18 nWR/GPIO17 CLR_INBUFF_FULL Fig.1 - Input Data Latch Reset Internal Data Bus (1 of 16) ADDR/GPIO19 nCS/GPIO18 Fig.2 - Output Data Enable nRD/GPIO16 SD15-0
D
Q
INBUFF_FULL (Reg 0xC0C2 Bit1)
Figure 3-2. Functional Logic Diagram
3.17
Mailbox Interface
The mailbox interface is accessed through three registers: 1. INBUFF Data Register (0xC0C4; SL11R Read) 2. OUTBUFF Data Register (0xC0C4; SL11R Write) 3. STATUS Register (0xC0C2: Read Only) When data is transferred to the SL11R through the Mailbox Interface, the external system must perform the transfer based on the values in the status register. When a word is written to the SL11R, the `IF' (INBUFF FULL) bit in the status register (0xC0C2) is set by the SL11R hardware. This bit must be polled until it is cleared to `0' by the SL11R. This indicates that the word has been accepted by the SL11R and that it is ready for another word. When data is read from the SL11R, the `OF' (OUTBUFF FULL) bit in the status register will be set by the SL11R when valid data is available. When the data is read by the external system, this bit will be cleared by the SL11R hardware. When a new word is available, the OF bit will again be set.\
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3.18
DMA Interface
This interface uses the same hardware as the Mailbox Interface, except that the DMA engine inside the SL11R generates DMA requests to control the transfer. Because the DMA engine handles the transfer of data through the Input and Output buffer, there is no need for the external system to poll the status register. The external system simply waits for a DREQ (GPIO 20) from the SL11R and transfers data. The SL11R DMA engine can transfer data in only one direction at a time. Please note that only 16-bit DMA transfers are supported on the SL11R. The 22-bit DMA counter is loaded through registers 0xC02C and 0xC02E. This makes up the DMA start address and the location of the first word to be written or read. The 22-bit DMA end address register is loaded through registers 0xC030 and 0xC032. This will be location of the last word written into the SL11R. When reading data out of the SL11R, the end address register should be loaded with the last address to be read from plus two. After these registers are loaded, the DMA control register (0xC0C0) must be loaded with a 0x0007 to enable the DREQ output pin. Lastly, the other DMA control register (0xC02A) is loaded with either a 0x0001, to start DMA transfers into the SL11R, or 0x0003, to start DMA transfers out of the SL11R.
PCLK
tCDQ
DREQ/GPIO20
tDCS tAPW tRAH tCPW
ADDR/GPIO19
nCS/GPIO18
tDR tRPW
tRCH tRHDQ
nRD/GPIO16
tACC tRDH DATA VALID
SD15-0
Figure 3-3. Mailbox/DMA Read Parameter tCDQ tAPW tCPW tRPW tRAH tRCH tACC tDCS tDR tRHDQ tRDH Description PCLK to DREQ high ADDR pulse width nCS pulse width Read pulse width ADDR hold after read high nCS hold after read high Read access time DREQ high to CS low DREQ high to read low Read high to DREQ low hold Read high to data hold 5 5 30 10 Min. 1 30 30 30 0 0 25 Typical Max. 17 Unit ns ns ns ns ns ns ns ns ns ns ns
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PCLK
tCDQ
DREQ/GPIO20
tDCS tAPW tWAH tCPW
ADDR/GPIO19
nCS/GPIO18
tDW
tCWS tWRPW tWDH tDWS
tWCH tWHDQ
nWR/GPIO17
SD15-0
DATA VALID
Figure 3-4. Mailbox/DMA Write Parameter tCDQ tAPW tCPW tCWS tWRPW tWAH tWCH tDWS tDCS tWHDQ tDW tWDH Description PCLK to DREQ high ADDR pulse width nCS pulse width nCS low to write high setup Write pulse width ADDR hold after read high NCS hold after read high Data setup to write high setup DREQ high to CS low Write high to DREQ low hold DREQ high to write low Write high to data hold 5 5 Min. 1 20 20 10 10 5 5 10 5 30 Typical Max. 17 Unit ns ns ns ns ns ns ns ns ns ns ns ns
3.19
Fast DMA Mode
This mode is currently used by the DVC 8-Bit DMA and 8/16-Bit DMA modes. In the DVC 8-Bit DMA mode, the DMA data path will be 8-bits, which correspond to SD0-SD7. In the 8/16-Bit DMA mode, the DMA data path can be configured to either 8 or 16 bits.
3.20
SL11R Interface Modes
The SL11R has four modes. They are: General Purpose I/O mode, Fast EPP mode, 8-bit DMA mode, and 8/16-bit DMA Mailbox Protocol ports mode. These modes are shared and can be configured under software control. Note: The UART and 2-wire serial interface I/O pins are fixed in all cases.
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3.20.1 General Purpose IO mode (GPIO)
In the GPIO mode, the SL11R has up to 32 General-Purpose IO signals available. However, four pins that are used by the UART and the 2-wire serial interface that cannot be used as GPIO pins. A typical application for this GPIO is the Parallel Port to USB. The SL11R executes at 48MHz, which is fast enough to generate any Parallel Port timing. The SL11R also includes a special mode for EPP timing designed for special devices that have no delay in EPP mode. On any other available General Purpose programmable I/O, the pins can be programmed for peripheral control and/or status. Note: The Fast DMA and PWM Interfaces are not supported in this mode. 3.20.2 8/16-bit DMA Mode
This Mode includes the Mailbox Protocol and DMA Protocol. The Mailbox Protocol allows asynchronous exchange of data between the external Processor (i.e. DSP or other Microprocessor) and SL11R via SD0-SD15 (GPIO 0-15) which is a bidirectional data port. The DMA Protocol allows large blocks of data to be transferred to or from the SL11R via the 8/16-bit DMA port. 3.20.3 Fast EPP Mode
This mode is designed to interface with a special optimized high-speed EPP interface. In this mode, the SL11R processor has direct access to the EPP control port. Note: The Fast DMA and PWM Interface are not supported in this mode. 3.20.4 DVC 8-bit DMA Mode
This DVC 8-bit DMA mode is designed to interface with CCD cameras. Camera control and setup is performed through the serial control bus. The SL11R 16-bit processor has direct access to the control port and the camera operation is dependent on commands passed from the USB Host to the SL11R. Raw video data from the CCD Camera is input to the SL11R on the 8-bit video data bus (SD7-SD0) using a combination of clock, control signals and 8-bit DMA. Note: The PWM Interface is not supported in this mode.
4.0
4.1
Interface
Internal Masked ROM: 0xE800-0xFFFF
The SL11R has a built-in 3Kx16 internal masked ROM that contains software bootstrap code to allow programs in an external 8/16-bit ROM to be executed. The ROM code can also load data from the 2-wire serial interface into internal RAM for execution. In addition, the internal BIOS ROM contains the Interrupt Service Routines (see [Ref. 1] SL11R_BIOS for information) that support the USB, 2-wire serial interface, UART interfaces and Boot-Up options (Boot-up from 2-wire serial interface or External ROM). This SL11R BIOS ROM eases software development of all SL11R interfaces. The SL11R Chip is ready for all the USB enumeration and download/program code. The SL11R Internal Masked ROM (i.e. SL11R BIOS) is mapped from address 0xE800 to 0xFFFF. On power up or hardware reset, the SL11R processor jumps to the address of 0xFFF0, which contains a long jump to the beginning of the internal ROM of address 0xE800. See Table 4-1. Table 4-1. Internal Masked ROM (SL11R BIOS) Address 0xE800-0xFFEF 0xFFF0-0xFFF3 0xFFF4-0xFFF9 0xFFFA-0xFFFB 0xFFFC-0xFFFD 0xFFFE-0xFFFE 0xFFFF-0xFFFF Memory Description SL11R BIOS code/data space Jump to 0xE800 Reserved for future use. ROM BIOS Checksum SL11R BIOS Revision Peripheral Revision QT Engine Instruction Revision
4.2
External ROM: 0xC100-0xE800
The SL11R BIOS ROM reserves addresses from 0xC100 to 0xE800 for external ROM. During BIOS initialization, the SL11R will scan for the signature ID (0xCB36) at location 0xC100. After a valid signature is detected, execution will begin at address 0xC102 (see [Ref. 1] SL11R_BIOS for more information). The signal nXROMSEL is used to enable the external ROM. It is mapped from
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0xC100 to 0xE800 by default. However, the Extended Memory Control can be used to configure multiple windows for external ROM set-up. Note: The Address space from 0x8000-0xC100 can also be used as the external ROM (see the External Memory Control set-up for more detail).
4.3
Internal RAM: 0x0000-0x0BFF
The SL11R contains a 1.5Kx16 internal RAM. This memory is used to buffer video data and USB packets and is accessed by the 16-bit processor and the SIE (Serial Interface Engine). USB transactions are automatically routed to the memory buffer. The 16-bit processor has the ability to set up pointers and block sizes in buffer memory for USB DMA transactions. For example, video data can be read from the camera interface and is sent to the USB port by the internal DMA engine. The SL11R BIOS uses this internal RAM for USB buffers, BIOS variables and user data/code. Executable code or data can reside in multiple locations: internal masked ROM (3Kx16), internal RAM (3Kx8), external ROM and external SRAM. Program code or data can also be loaded to either the internal or the external RAM from the USB port, the RS232 port, or the 2-wire serial interface. The SL11R Internal RAM is mapped from 0x0000 to 0x0BFF. See internal RAM memory usage in Table 2 below: Table 4-2. Internal RAM Memory Usage Address 0x0000 - 0x00FF 0x0100 - 0x01FF 0x0200 - 0x021F 0x0220 - 0x0343
[2]
Memory Description Hardware/Software Interrupts Register Banks/USB Control/Software Stack Hardware Interrupts stack SL11R BIOS internal buffers & variables User's Programming Space
0x0344 - 0x0BFF
Note: 2. This address may be changed due to SL11R BIOS revision updates. The new SL11R BIOS may require more internal memory for its variable usage in any new SL11R BIOS.
* The addresses from 0x0000 to 0x00FF are reserved for hardware and software interrupt vectors (see [Ref. 1] SL11R_BIOS for more information). * Addresses from 0x0100 to 0x01FF are reserved for Internal Register Banks (SL11R register R0-R15 bank 0 and R0-R15 bank 1) and the software stack. Others are reserved for USB Control registers and other read/write control registers. * Addresses from 0x0200 to 0x021F are reserved for the hardware interrupt stack. * Addresses from 0x0220 to 0x0343 are available internal RAM for application software. Software can be downloaded via the USB port or UART interface (see [Ref. 1] SL11R_BIOS for more information).
4.4
Clock Generator
The SL11R has an option to use either a 48-MHz or 12-MHz external crystal or oscillator as its clock source. SL11R includes an internal PLL that can be configured by software. At power-up, the SL11R BIOS default configuration sets the processor clock to run at 2/3 of X1 (of the external provided clock). Example 1 Changing SL11R CPU Speed The default of the SL11R BIOS assumes a 48MHz input clock, so the SL11R processor clock is (2/3)*48MHz = 32MHz. See example below: mov mov [0xC006],0x10 [0xC008],0 ;clock = 2/3*X1 ;CPU clock at 32MHz
If the X1 input clock is 48 MHz, then the maximum speed of the SL11R processor can be set at follows: mov mov [0xC006],0 [0xC008],0 ;clock = set up at X1 clock input ;CPU clock at 48MHz
If the X1 input clock is 12 MHz, then the maximum speed of the SL11R processor can be set to: mov mov [0xC006],0x40 [0xC008],0 ;clock = 4*X1 ;CPU clock at 48MHz
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X1
X2
Rf 1M Rs 100 X1
48 MHz, series, 20-pF load Cbk 0.01 F Cout 22 pF
Lin 2.2 - 3.3 H
Figure 4-1. 48-MHz Crystal Circuit
X1
X2
Rf 1M Rs 2.7K X1
12 MHz, series, 20-pF load Cin 22 pF Cout 22 pF
Figure 4-2. 12-MHz Crystal Circuit Note: You need to set bit C2 =1 from configuration address (0xC006). See section 4.5 for CPU control speed. Document #: 38-08006 Rev. ** Page 17 of 85
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4.5
USB Interface
The SL11R has a built-in transceiver that meets the USB specification v1.1. The transceiver connects directly to the physical layer of the USB engine. It is capable of transmitting or receiving serial data at the USB maximum data rate of 12 Mbits/sec. The SL11R has four USB DMA engines for four USB endpoints. Each of the USB DMA engines is independently responsible for its respective USB transaction. The 16-bit processor has the ability to set up pointers and block sizes in buffer memory for USB transactions. The SL11R Controller contains a number of Registers that provide overall control and status functions for USB transactions. The first set of registers is for control and status functions, while the second group is dedicated to specific endpoint functions. Communication and data flow on the USB is implemented using endpoints. These uniquely identifiable entities are the terminals of communication flow between a USB host and USB devices. Each USB device is composed of a collection of independently operating endpoints. Each endpoint has a unique identifier: the endpoint number. (See USB specification v1.1. Sec 5.3.1) The SL11R also includes the SL11R BIOS that provides a set of subroutines via interrupt calls for all USB interface functions required to communicate with a USB host (refer to [Ref. 1] SL11R_BIOS for more information). The SL11R BIOS greatly simplifies the firmware/software development cycle. 4.5.1 USB Global Control & Status Register (0xC080: R/W)
The USB Global Control & Status Register allows high-level control and provides status of the USB-DMA engines. The Global Control & Status register bits are defined as follows: D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 0 D8 0 D7 0 D6 0 D5 0 D4 0 D3 UA D2 US D1 UR D0 UE
D15-D4 D0 D1 D2 D3
Reserved UE UR US UA USB Enable = '1', Overall USB enable/disable bit USB Reset USB SOF = '1', USB received Reset command = '1', USB received SOF command
USB Activity = '1', Activity Seen
Notes: * Suspend state should be entered if there is no activity after 3mS (UA). * The US and UA bits are automatically cleared after they are read by the SL11R processor. * D15-D4 are the reserved bits, should be written with zeros. * The SL11R BIOS will set the UE=1 upon reset. 4.5.2 USB Frame Number Register (0xC082: Read Only)
The Frame Number Register contains the 11-bit ID Number of the last SOF received by the device from the USB Host. D15 0 D14 0 D13 0 D12 0 D11 0 D10 S10 D9 S9 D8 S8 D7 S7 D6 S6 D5 S5 D4 S4 D3 S3 D2 S2 D1 S1 D0 S0
D15-D11 D10-D0
Reserved S10-S0
set to all zeros. SOF ID Number of last SOF Received
Note: * The SL11R BIOS uses this register to detect USB activity for the internal idle task. 4.5.3 USB Address Register (0xC084: R/W)
Address Register holds the USB address of the device assigned by the Host - initialized to address 0x0000 upon Power up. D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 0 D8 0 D7 0 D6 A6 D5 A5 D4 A4 D3 A3 D2 A2 D1 A1 D0 A0
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D15-D7 D6-D0 Reserved A6-A0 set to all zeros USB Address of device after assignment by Host
Note: * The SL11R BIOS modifies this register upon receiving the SET_ADDRESS from the host. (See [Ref. 3] Universal Serial Bus Specification 1.1, Chapter 9 for more information) 4.5.4 USB Command Done Register (0xC086: Write Only)
This is the USB command done register. It is only used by the control point (endpoint 0).
D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 0 D8 0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 E
D15-D1 D0
Reserved E
set to all zeros. Set E=0 for Successful Command Completion Set E=1 for Error Command Completion
Note: * The SL11R BIOS modifies this register upon command completion on endpoint 0.
4.6
USB Endpoint 0 Control & Status Register (0xC090: R/W)
See the USB Endpoint 3 Control & Status Register for more information.
4.7
USB Endpoint 1 Control & Status Register (0xC092: R/W)
See the USB Endpoint 3 Control & Status Register for more information.
4.8
USB Endpoint 2 Control & Status Register (0xC094: R/W)
See the USB Endpoint 3 Control & Status Register for more information.
4.9
4.9.1
USB Endpoint 3 Control & Status Register (0xC096: R/W)
General Description for All Endpoints from Endpoint 0 to Endpoint 3
The SL11R Controller supports four endpoints. Endpoint 0 is the default pipe and is used to initialize and control the peripheral device. It also provides access to the peripheral device's configuration information, and supports control transfers. Endpoint 1, 2, and 3 support interrupt transfers, bulk transfers up to 64 Bytes/packet, or Isochronous transfers up to 1024 Bytes/packet size. 4.9.2 USB Endpoints Control (For Writing)
Each of the endpoint Control Registers when written have the following functions assigned: Bit Position D0 D1 D2 D3 D4 D5 D6-D15 Bit Name ARM Enable DIR ISO Stall Zero Length Not Defined Function Allows enabled transfers when set to '1'. Cleared to '0' when transfer is complete When set to `1' it allows transfers to this endpoint. When set to '0' USB transactions are ignored. If enable = '1' and Arm = '0', the endpoint will return NAK to USB transmissions. When set to `1', It transmits to Host (IN). When '0' receive from Host (OUT) When set to '1' It allows Isochronous mode for this endpoint When set to `1' It sends Stall in response to next request on this endpoint When set to `1' It sends a zero length packet Set to logic `0's
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4.9.3 USB Endpoints Status (For Reading)
Reading the Endpoint Status Register provides Status information relative to the packet that has been received or transmitted. The register is defined as follows: Bit Position D0 D1 D2 D3 D4 D5-D12 D13 D14 D15 Bit Name Arm Enable DIR ISO Stall Not used Setup Error Done If '1', the endpoint is armed If '1', the endpoint is enabled Direction bit. If '1', set to transmit to Host (IN). If '0', set to receive from Host (OUT) If `1', isochronous mode selected for this endpoint If '1', endpoint will send stall on USB when requested Read returns logic `0's If '1', a Setup packet has been received If '1', an error condition occurred on last transaction for this endpoint If '1', transaction completed. Arm Bit is cleared to '0' when Done Set Function
Notes: * Endpoint 0 is set up as a control endpoint. The DIR bit is read-only, and indicates the direction of the last completed transaction. If the direction is incorrect, it is the firmware's responsibility to handle the error. On other endpoints, DIR bit is written, and if the direction of the transfer does not match the DIR bit, then the transaction is ignored. * At the end of any transfer to an armed and enabled endpoint (with the correct DIR bit), an interrupt occurs, and vectors to a different location depending upon whether an error occurred or not. At the end of this transfer, the corresponding endpoint is disarmed (the Arm bit is cleared), and the DATA0/DATA1 toggle bit is advanced if no error occurred. If a packet is received with an incorrect toggle state, the packet is ignored so that the host will re-send the data. * The DATA0/DATA1 bit is automatically toggled by the hardware. To reset this DATA0/DATA1 toggle bit to DATA0, the Enable on the D1 bit should be cleared to `0' and then set to `1'. * When the Zero Length bit (D5) is set, the host will receive the zero length USB packet, regardless of the number of bytes in the USB Count register. * The SL11R BIOS has full control of USB endpoint 0. The SL11R BIOS responds to all numeration from the host. On other endpoints, the SL11R BIOS can be used to control under BIOS interrupt calls (see [Ref. 1] SL11R_BIOS). * The SL11R BIOS will set all USB Control & Status registers for endpoint 1 through 3 to zero upon receiving the SET_CONFIG command from host. (See [Ref. 3] Universal Serial Bus Specification 1.11, Chapter 9 for more information.) 4.9.4 USB Endpoint 0 Address Register (0x0120: R/W)
This is the pointer to memory buffer location for USB reads and writes to this Endpoint. At the end of any transfer, this register will contain its original value plus the value in the USB Endpoint Count Register. 4.9.5 USB Endpoint 1 Address Register (0x0124: R/W)
See USB Endpoint 0 Address Register (0x0120: R/W) 4.9.6 USB Endpoint 2 Address Register (0x0128: R/W)
See USB Endpoint 0 Address Register (0x0120: R/W) 4.9.7 USB Endpoint 3 Address Register (0x012C: R/W)
See USB Endpoint 0 Address Register (0x0120: R/W) 4.9.8 USB Endpoint 0 Count Register (0x0122: R/W)
This register is used to set the maximum packet size for the USB transfer. At the end of a successful transfer, the USB endpoint Count Register is set to zero. 4.9.9 USB Endpoint 1 Count Register (0x0126: R/W)
See USB Endpoint 0 Count Register (0x0122: R/W) 4.9.10 USB Endpoint 2 Count Register (0x012A: R/W)
See USB Endpoint 0 Count Register (0x0122: R/W)
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4.9.11 USB Endpoint 3 Count Register (0x012E: R/W)
See USB Endpoint 0 Count Register (0x0122: R/W)
4.10
Processor Control Registers
The SL11R provides software control registers that can be used to configure the chip mode, clock control, read software version and software breakpoint control. 4.10.1 Configuration Register (0xC006: R/W)
The Configuration Register is used to configure the SL11R into the appropriate mode, and to select a clock multiplier. D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 0 D8 0 D7 0 D6 C2 D5 C1 D4 C0 D3 CD D2 M1 D1 M0 D0 MD
Note: D6-4 and C2-0 are Clock Configuration bits. These bits select the clock source. The clock may come from an outside pin (X1 or X_PCLK) or it may come from the PLL multiplier as indicated in the table. C2 0 0 0 0 1 1 1 1 D3 C1 0 0 1 1 0 0 1 1 C0 0 1 0 1 0 1 0 1 PCLK X1 2/3*X1 X_PCLK 2/3*X1 4*X1 8/3*X1 4*X1 8/3*X1 CD RCLK X1 X1 X1 X1 4*X1 4*X1 4*X1 4*X1 OE 0 0 0 1 0 0 1 1
If Clock Disable bit = `1', this Clock Configuration register can no longer be modified through software writes. It is a "sticky bit" used to lock the configuration through a write to this bit in the boot prom code. Note: * On the SL11R chip set, this bit will be set to zero. * There are four modes defined in this documentation: DVC 8-bit DMA mode, Fast EPP mode, 8/16-bit DMA mode and General Purpose IO (GPIO) mode. All modes are pin-compatible. D2, D1 M1,M0: SL11R modes are selected as shown here: M1 0 0 1 1 D0 M0 0 1 0 1 MD Mode GPIO DVC 8-Bit DMA Fast EPP 8/16-Bit DMA
If Mode Disable bit = `1', this Configuration register can no longer be modified through software writes. It is a "sticky bit" used to lock the configuration through a Write to this bit in the boot prom code. Note: By default, this bit will be set to zero by the SL11R BIOS. D15-D7 Reserved should be set to all zeros.
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Where: PCLK RCLK OE is connected to the SL11R processor clock. is the resulting clock that connects to other modules (i.e. PWM, USB engine). when OE=1, the X_PCLK (pin 59) will become an output pin of the PCLK value.
Notes: * When the X1 input pin is fed with a 12 MHz signal, the software should set C2 to `1' to enable the PLL. * X_PCLK is a bidirectional pin allowing an additional clock input for PCLK when selected or an observation pin for PCLK when OE = `1'. * The X_PCLK can be used as the input clock like X1, but only when mode C2=0, C1=1, C0=0. * Upon reset, the SL11R BIOS will set this register equal to 0x0010 (i.e. C2=0, C1=0, C0=1, PCLK=X1, RCLK=X1, OE=0, M1-M0=0=GPIO Mode). 4.10.2 Speed Control Register (0xC008: R/W)
The Speed Control Register allows the SL11R processor to operate at a number of speed selections. A four-bit divider (SPD3-0 + 1) selects the speed as shown below. Speed will also depend on the clock multiplier. See Configuration Register (0xC006: R/W) for more information. D15-D4 0 D3-D0 SPD3-SPD0 D3 SPD3 D2 SPD2 D1 SPD1 D0 SPD0
Speed selection bits SPD3-0 SL11R Speed
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
D15-D4 Note: Reserved
48.00 MHz. 24.00 MHz. 16.00 MHz. 12.00 MHz. 09.60 MHz. 08.00 MHz. 06.86 MHz. 06.00 MHz. 05.33 MHz. 04.80 MHz. 04.36 MHz. 04.00 MHz. 03.69 MHz. 03.42 MHz. 03.20 MHz. 03.00 MHz.
should be set to all zeros.
Upon reset, the lowest speed is selected for low power operation. The SL11R BIOS will configure the clock to 24MHz as part of its initialization.
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4.10.3 Power Down Control Register (0xC00A: R/W)
During Power down mode, the peripherals are put in a "pause" state. All counters and timers stop incrementing and the PWM stops. D15-D6 0 D5 USB D4 GPIO D3 PUD1 D2 PUD0 D1 SUSPEND D0 HALT
There are two ways to enter power-down mode: Suspend or Halt. D5 D4 D3-D2 USB GPIO PUD1-PUD0 Enable restarts on USB transition resulting in device power up. Enable restarts on GPIO transition resulting in device power up (See GPIO Interrupt Control Register (0xC01C:R/W)). Power Up Delay Selection. Four delays are provided and selected using these select bits. This is time from power up until processor starts executing allowing clock to settle. PUD1 0 0 1 1 PUD0 0 1 0 1 Power-up Delay 0 milliseconds 1 milliseconds 8 milliseconds 64 milliseconds
D1 D0 D15-D6 4.10.4
SUSPEND HALT Reserved
To save power, Suspend mode stops all clocks in the SL11R. ends with an interrupt. should be set to all zeros.
This mode ends with a transition on either USB or any Interrupt. It is followed by a delay set in the Power-up delay bit fields.
Breakpoint Register (0xC014: R/W)
The Breakpoint Register holds the breakpoint address. Access to this address causes an INT127. D15 A15 D14 A14 D13 A13 D12 A12 D11 A11 D10 A10 D9 A9 D8 A8 D7 A7 D6 A6 D5 A5 D4 A4 D3 A3 D2 A2 D1 A1 D0 A0
D15-0
A15-0
Breakpoint address.
4.11
Interrupts
The SL11R provides 127 interrupt vectors. The first 64 vectors are hardware interrupts and the next 64 are software interrupts (see the [Ref. 1] SL11R_BIOS for more information).
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4.11.1 Hardware Interrupts
The SL11R allocates addresses from 0x0000 to 0x003E for hardware interrupts. The hardware interrupt vectors are shown below: Table 4-3. Hardware Interrupt Table Interrupt Number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19-63 Vector Address 0x0000 0x0002 0x0004 0x0006 0x0008 0x000A 0x000C 0x000E 0x0010 0x0012 0x0014 0x0016 0x0018 0x001A 0x001C 0x001E 0x0020 0x0022 0x0024 0x0026- 0x003E Timer0[3] Timer1[4] GP IRQ0[4] GP IRQ1[4] UART Tx[3] UART Rx[3] Fast DMA Done[4] USB Reset USB SOF[5] USB Endpoint0 No Error[3] USB Endpoint0 Error[3] USB Endpoint1 No Error USB Endpoint1 Error USB Endpoint2 No Error USB Endpoint2 Error USB Endpoint3 No Error USB Endpoint3 Error 8/16-bit DMA Mode Mailbox TX Empty[4] 8/16-bit DMA Mode Mailbox RX Full[4] Reserved Interrupt Type
Notes: 3. These hardware interrupt vectors are reserved for internal SL11R-BIOS usage. You should not attempt to overwrite these functions. 4. These hardware interrupt vectors are initialized to return on the interrupt. 5. The SOF interrupt is generated when there is an incoming SOF on the USB.
All these vector interrupts are read/write accessible. You can overwrite these default software interrupt vectors by replacing your interrupt service subroutine. The addresses from 0x0000 to 0x003E are read/write accessible and can be used for variables. 4.11.2 Interrupt Enable Register (0xC00E: R/W)
This is a global hardware interrupt enable register that allows control of the hardware interrupt vectors. The SL11R BIOS default set-up of this register is 0x28 (i.e. USB and UART bits are set). D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 0 D8 0 D7 0 D6 MBX D5 USB D4 FDMA D3 UART D2 GP D1 T1 D0 T0
D6 D5 D4 D3
MBX USB FDMA UART
Mail Box interrupt enable (8/16-bit DMA Mode Only) USB Interrupt enable Fast DMA Done Interrupt enable UART Interrupt enable Page 24 of 85
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D2 D1 D0 4.11.3 GP T1 T0 Timer1 Interrupt Enable Timer0 Interrupt Enable
General Purpose I/O pins Interrupt enables (see GPIO Interrupt Control Register (0xC01C: R/W))
GPIO Interrupt Control Register (0xC01C: R/W)
This register defines the polarity of the GPIO interrupt on IRQ1 (GPIO25) and IRQ0 (GPIO24). The GPIO bit on the Interrupt Enable Register must be set in order for this register to operate. D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 0 D8 0 D7 0 D6 0 D5 0 D4 0 D3 P1 D2 E1 D1 P0 D0 E0
D3 D2 D1 D0 Note:
P1 E1 P0 E0
IRQ1 polarity is rising edge if "1", falling edge if "0" Enable IRQ1 if set to "1" IRQ0 polarity is rising edge if "1", falling edge if "0" Enable IRQ0 if set to "1"
The interrupts can be enabled for "Suspend mode" by the power down Register or enabled for interrupts by the Interrupt Enable Register. 4.11.4 Software Interrupts
The SL11R allocates addresses from 0x0040 to 0x00FE for software interrupts. The software interrupt vectors are shown in Table 4-4:
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Table 4-4. Software Interrupt Table Interrupt Number 64 (0x40) 65 (0x41) 66 (0x42) 67 (0x43) 68 (0x44) 69 (0x45) 70 (0x46) 71 (0x47) 72 (0x48) 73 (0x49) 74 (0x4a) 75 (0x4b) 76 (0x4c) 77 (0x4d) 78 (0x4e) 79 (0x4f) 80 (0x50) 81 (0x51) 82 (0x52) 83 (0x53) 84 (0x54) 85 (0x55) 86 (0x56) 87 (0x57) 88 (0x58) 89 (0x59) 90 (0x5a) 91 (0x5b) 92 (0x5c) 93 (0x5d) 94 (0x5e) 95 (0x5f) 96 (0x60) 97 - 104 105 (0x69) 106-109 110-124 125-127 Vector Address 0x0080 0x0082 0x0084 0x0086 0x0088 0x008A 0x008C 0x008E 0x0090 0x0092 0x0094 0x0096 0x0098 0x009A 0x009C 0x009E 0x00A0 0x00A2 0x00A4 0x00A6 0x00A8 0x00AA 0x00AC 0x00AE 0x00B0 0x00B2 0x00B4 0x00B6 0x00B8 0x00BA 0x00BC 0x00BE 0x00C0 0xC2-0xD0 0x00D2 0xD4-0xDA 0xDE-0xF8 0xFA-0xFE 2-wire serial interface_INT UART_INT[6] SCAN_INT[6] ALLOC_INT[6] Data: start of free memory. Default=0x200[7] IDLE_INT IDLER_INT INSERT_IDLE_INT PUSHALL_INT[6] POPALL_INT[6] FREE_INT[6] REDO_ARENA[6] HW_SWAP_REG[6] HW_REST_REG[6] SCAN_DECODE_INT USB_SEND_INT[6] USB_RECEIVE_INT[6] Reserved USB_STANDARD_INT Data: Standard loader vector. Defaut=0[7] USB_VENDOR_INT Data: USB_Vendor loader. Default = 0xff[7] USB_CLASS_INT Data: USB_Class_Loader. Default = 0[7] USB_FINISH_INT Data: Device Descriptor. Default = Cypress Device Desc[7] Data: Configuration Desc. Default = Cypress Configuration[7] Data: String Descriptor. Default = Cypress String Desc.[7] USB_PARSE_CONFIG_INT USB_LOADER_INT USB_DELTA_CONFIG_INT USB_PULLUP_INT Reserved for future addition secondary USB Port POWER_DOWN_SUBROUTINE Reserved for future secondary USB Port User's ISR or internal peripheral interrupt Reserved for the Debugger
[6]
Interrupt Type Reserved for future extension of other Serial EEPROM
Notes: 6. These software vectors are reserved for the internal SL11R-BIOS. The user should not overwrite these functions. 7. These vectors are used as the data pointers. The user should not execute code (i.e. JMP or INT) to these vectors. See [Ref. 1] SL11R_BIOS for more information.
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All these vector interrupts are read/write accessible. User can overwrite these default software interrupt vectors by replacing the user's interrupt service subroutine.
4.12
UART Interface.
The SL11R Controller UART port supports a range of baud rates from 900 Baud up to 115.2K Baud. Baud Rate selection is made in the UART Control Register. Buffer status can be monitored in the UART Status Register. Transmit and receive data is written or read from the UART data register. The UART timers are independent of the general-purpose timers. The UART will cause "edge trigger" type interrupts when the receive buffer becomes FULL or the transmit buffer becomes EMPTY. The SL11R BIOS uses the UART port for the software debugging process. It is recommended that the user include this interface in their hardware design. A simple 4-pin header may be used to connect to a serial cable equipped with a MAX202 transceiver.
BQDP!'AAAA
7; *1' 5;
VCC
BI9AAAAA!
0$;
3&
BQDP!&AAAA" W88AAAA#
Figure 4-3. UART Port Connection The SL11R BIOS uses GPIO28 for data transmit (TX) and GPIO27 for data receive (RX). These two pins cannot be used for any other purpose. Note: On reset, the SL11R BIOS will configure the UART to operate at 14,400 baud. Other parameters are: 1 stop bit, 8 data bits, no parity. 4.12.1 UART Control Register (0xC0E0: R/W)
The SL11R allocates two General Purpose I/O signals for the UART function. They are GPIO28 (UART_TXD) and GPIO27 (UART_RXD). On reset, the SL11R BIOS will default this register to the value of 0x000b (i.e. UART Enable and Baud = 14.4K Baud). D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 0 D8 0 D7 0 D6 0 D5 0 D4 DIV8 D3 B2 D2 B1 D1 B0 D0 E
D15-D5 D4 D3-1 Baud Rate 000 001 010 011 100 101 110 111
Reserved bits DIV8
Set to all zeros. Acts as a pre-scaler if set to `1', divides the clock by 8 before generating the UART clock.
B2-0 Selector Bits. 115.2K Baud 57.6K Baud 38.4K Baud 28.8K Baud 19.2K Baud 14.4K Baud 9.6K Baud 7.2K Baud with /8 Prescaler 14.4K Baud 7.2K Baud 4.8K Baud 3.6K Baud 2.4K Baud 1.8K Baud 1.2K Baud 0.9K Baud
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D0 4.12.2 E Enable UART when set = '1'. When '0' UART pins are GPIO.
UART Status Register (0xC0E2: Read Only)
This register is used by the SL11R BIOS to detect the UART status function via RXF and TXE flags.
D15-D7 0
D6 0
D5 0
D4 0
D3 0
D2 0
D1 RXF
D0 TXE
D15-D2 D1 D0
Reserved bits RXF TXE
Set to all zeros. Receive Buffer Full Flag. Transmit Buffer Empty Flag. Set to `1' when data moves from buffer to output shift register.
Note: No error detection for received data is supported. 4.12.3 UART Transmit Data Register (0xC0E4: Write Only)
This register is used by the SL11R BIOS to send data to the host. D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 0 D8 0 D7 TR7 D6 TR6 D5 TR5 D4 TR4 D3 TR3 D2 TR2 D1 TR1 D0 TR0
D7-D0 4.12.4
TR7-0
UART Transmit Data
UART Receive Data Register (0xC0E4: Read Only)
This register is used by the SL11R BIOS to receive data from the host. D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 0 D8 0 D7 RD7 D6 RD6 D5 RD5 D4 RD4 D3 RD3 D2 RD2 D1 RD1 D0 RD0
D7-D0
RD7-0
UART Receive Data.
4.13
Serial EEPROM Interface (2-wire serial interface)
The SL11R provides an interface to an external serial EEPROM. The interface is implemented using General Purpose I/O signals. A variety of serial EEPROM formats can be supported: currently the BIOS ROM supports the two-wire serial EEPROM type. The serial EEPROM can be used to store specific Peripheral USB configuration and add on value functions. It can also be used for field product upgrades The SL11R BIOS uses an interrupt to read and write from/to an external serial EEPROM. The recommended serial EEPROM device is a 2-Wire Serial CMOS EEPROM (AT24CXX Device Family). Currently, the SL11R BIOS Revision 1.1 allows reading/writing to/from EEPROM, up to 2K Bytes (16K bits), 2-wire serial interface device (i.e. AT24C16). The user's program and USB vendor/device configuration can be programmed and stored into the external EEPROM device. On power up the content of the EEPROM will be downloaded into RAM and may be executed as code or used as data, or both. The advantage of the 2-wire serial interface/EEPROM interface is the space and cost saving when compared to using an external 8-bit PROM/EPROM. The SL11R BIOS uses two GPIO pins, GPIO31 and GPIO30 to interface to an external serial EEPROM (see Figure 4-4): * GPIO31 is connected to the Serial Clock Input (SCL). * GPIO30 is connected to the Serial Data (SDA). * We recommend you add a 5K to 15K pull-up resistor on the Data line (e.g. GPIO30). Document #: 38-08006 Rev. ** Page 28 of 85
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* Pin 1 (A0), Pin 2 (A1), Pin 3 (A2), Pin 4 (GND) and Pin 7 Write Protect) are connected to Ground.
VCC
EEPROM
1 2 3 4 A0 A1 A2 GND VCC WP SCL SDA 8 7 6 5 GPIO31 GPIO30 5K 0.1uF
AT24C16
Figure 4-4. 2-Wire Serial Interface 2K-byte Connection The current SL11R BIOS only support up to a 2Kbyte serial EEPROM. To read and write to a device that is larger than 2Kbytes, the SL11R-BIOS requires additional serial EEPROM to be connected as shown in Figure 4-5.
VCC
EEPROM
1 2 3 4 A0 A1 A2 GND VCC WP SCL SDA 8 7 6 5 GPIO30 GPIO31 5K 0.1uF
AT24C128
Figure 4-5. 2-Wire Serial Interface 16K Connection In this example, the SL11R BIOS will first access the (small) program residing on IC1 serial EEPROM, and then it will access the second IC2 EEPROM (see [Ref. 1] SL11R_BIOS for more information).
4.14
External SRAM, EPROM, DRAM
The SL11R has a multiplexed address port and 16-bit data port. These interface signals are provided to interface to an external SRAM, ROM or DRAM. The DRAM port provides RAS, CAS, RD and WR control signals for data access and refresh cycles to the DRAM. At boot up stage, the SL11R BIOS configures the SL11R for external SRAM and serial EEPROM. In addition, the external memory interface is set up as 16-bit and 7 wait states for both external SRAM and EEPROM. The DRAM controller needs to be set up by the user. Example 2 SL11R extended memory setup: internal_rom_start: mov cmp je mov mov mov cmp je cmp jne or [0xC03A],0x0077 0xC102 [0xC006],0x10 [0xC008],1 [0xC03E],3 xrom_ok b[0xC100],0xB6 xrom_ok [0xC03A],0x80 ;set for 8-bit ROM ;check 0xc3b6 for 8-bit ROM ;set 16-bit ROM & 7 wait ;if it's there, jump to it ;2/3 clock ;at 24 MHz ;extra wait state for ROM and Debug [0xC100],0xCB36 ;check for special pattern in external ROM
[0xC100],0xC3B6 ;external ROM has 0xC3B6 as first 16 bits
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xrom_ok: mov cmp je or xram_ok: Note: The external memory devices can be 8 or 16 bits wide, and can be programmed to have up to 7 wait-states. External SRAM/PROM requires one wait state. 4.14.1 Memory Control Register (0xC03E: R/W) [0xC00],0xC3B6 [0xC00],0xC3B6 xram_ok [0xC03A],8 ;set for 8-bit external RAM ;check 0xC3B6 for 16-bit RAM
This register provides control of Wait States for the internal RAM and ROM. D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 0 D8 0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 RA D1 RO D0 DB
D2 D1 D0 4.14.2
RA RO DB
If `1', one-wait state for internal RAM is added If `1', one-wait state for internal ROM is added If `1', DEBUG mode is enabled. Internal address bus is echoed to external address pins.
Extended Memory Control Register (0xC03A: R/W)
This register provides control of Wait States for the external SRAM/DRAM/EPROM.
D15 0
D14 0
D13 0
D12 RM
D11 EM3
D10 EM2
D9 EM1
D8 EM0
D7 RO3
D6 RO2
D5 RO1
D4 RO0
D3 RA3
D2 RA2
D1 RA1
D0 RA0
D12 D11 D10-8 D7 D6-4 D3 D2-0 Note:
RM EM3 EM2-0 RO3 RO2-0 RA3 RA2-0
ROM Merge. If `1', nXROMSEL is active if nXMEMSEL is active. Extended Memory Width ('0' = 16, '1' = 8) Extended Memory Wait states (0 - 7) External ROM Width ('0' = 16, '1' = 8) External ROM wait states (0 - 7) External RAM Width ('0' = 16, '1' = 8) External RAM Wait States (0 - 7)
The default Wait State setting on power up or reset is 7 wait states. 4.14.3 Extended Page 1 Map Register (0xC018: R/W)
This register contains the Page 1 high order address bits. These bits are always appended to accesses to the Page 1 Memory mapped space. The default is 0x0000. D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 0 D8 A21 D7 A20 D6 A19 D5 A18 D4 A17 D3 A16 D2 A15 D1 A14 D0 A13
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If Bit A21 is `1', If bit A21 is `0' D8-0 A21-13 Page 1 high order address bits. The address pins on A21-A13 will reflect the content of this register when SL11R accesses the address 0x8000-0x9FFF. 4.14.4 Extended Page 2 Map Register (0xC01A: R/W) Page 1 reads/writes will access external DRAM Page 1 reads/writes will access some other external area (SRAM, ROM or peripherals). nXMEMSEL will be the external Chip Select for this space.
This register contains the Page 2 high order address bits. These bits are always appended to accesses to the Page 2 Memory mapped space. The default is 0x0000. D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 0 D8 A21 D7 A20 D6 A19 D5 A18 D4 A17 D3 A16 D2 A15 D1 A14 D0 A13
If Bit A21 is `1', If bit A21 is `0'
Page 2 reads/writes will access external DRAM Page 2 reads/writes will access some other external area (SRAM, ROM or peripherals) and nXMEMSEL will be the external Chip Select for this space.
D8-0
A21-13 Page 2 high order address bits. The address pins on A21-A13 will reflect the content of this register when SL11R access the address 0xA000-0xBFFF.
4.14.5
DRAM Control Register (0xC038: R/W)
A multiplexed address port and 16-bit data port are provided to interface to an external 256Kx16 or a 1Megx16 EDO DRAM. The port provides nRAS, nCASL, nCASH, nDRAMWR and nDRAMOE control signals for data access and refresh cycles to the DRAM. This register is designed to control the DRAM interface. D15-D7 0 D6 0 D5 0 D4 0 D3 0 D2 DT D1 PE D0 RE
D2 D1 D0
DT PE RE
DRAM Turbo, Enable when set = '1'. Uses 1 clock for CAS instead of 2. DRAM Page Mode Enable when set = '1'. DRAM Refresh Enable when set = '1'.
Note: * Most of EDO and Page mode DRAM can be used as long as the CAS signal is issued before the RAS signal. * Page mode access allows multiple CAS addresses to be issued within 1 Row address. The Page really corresponds to the Row. Once the Row address has been accessed, any accesses to that Page can be made without issuing the Row address again. Only the Column address is necessary. This allows for faster read and write accesses to the same page. 4.14.6 Memory Map
The total memory space allocated by the SL11R is 64K-bytes. Program, data, and I/O space are contained within a 64K-byte address space. The program code or data can be stored in either external RAM or external ROM. The SL11R allows extended data (video) to be stored on an external EDO DRAM. The entire (video image) data can be transferred via DMA directly to DRAM without software intervention. The total DMA size can be up-to 2M-bytes. The SL11R processor can access DRAM data via the address space from 0x8000 to 0xBFFF. The SL11R Controller provides a 16-bit Memory interface that can support a wide variety of external DRAM, RAM and ROM devices. The SL11R Controller memory space is byte addressable and is divided as follows:
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Table 4-5. Memory Map Function Internal RAM External RAM Extended Page 1/DRAM Extended Page 2/DRAM Memory Mapped Registers External ROM Internal ROM Address 0x0000 - 0x0BFF 0x0C00 - 0x7FFF[8] 0x8000 - 0x9FFF 0xA000 - 0xBFFF 0xC000 - 0xC0FF 0xC100 - 0xE7FF[9] 0xE800 - 0xFFFF
Each External memory space can be 8 or 16 bits wide, and can be programmed to have up to 7 wait-states.
Notes: 8. The External RAM address from 0x0000 to 0x0C00 will not be accessible from the SL11R processor. This is an overlay memory space between internal RAM and external RAM. The addressable external RAM will occupy from 0x0C00-0x7FFF, which is 29K-byte. The signal name nXRAMSEL on SL11R-pin56 will be active when the CPU access address from 0x0C00 to 0x7FFF.
Unused Overlay Memory Space 0x0000 to 0x0C00
Actual External RAM 0x0C00 to 0x7FFF SRAM (16Kx16) or
9.
When bit 12 (ROM Merge Bit) of the Extended Memory Controller Register at address 0xC03A is `0', then the External ROM address space will be mapped from 0xC100 to 0xE7FF. The address from 0x8000 to 0xC100 and the address from 0xE800 to 0xFFFF are the overlay memory spaces. The actual total size of the external ROM will be (0xE800-0xC100), which is 9.75K-byte. The signal nXROMSEL on the SL11R (pin57) will be active when the CPU accesses the address from 0xC100 to 0xE7FF. The signal nXMEMSEL on the SL11R (pin58) will be active when the CPU accesses the address from 0x8000 to 0xBFFF. When bit 12 (ROM Merge Bit) of the Extended Memory Controller Register at address 0xC03A is `1', then the External ROM address space will be mapped into these windows: 0x8000 to 0xBFFF and 0xC100 to 0xE7FF. The address from 0xC000 to 0xC100 and the address from 0xE800 to 0xFFFF are the overlay memory spaces. The actual total size of the external ROM will be (0xC000-0x8000) and (0xE800-0xC100), which is 16K-byte + 9.75K-bytes, or 25.75K.
Bit 12 (ROM Merge) of the Extended Memory
Bit 12 (ROM Merge) of the Extended Memory
Controller Register = 0
Unused Overlay Memory Space 0x8000 to 0x9FFF Unused Overlay Memory Space 0xA000 to 0xBFFF Unused Overlay Memory Space 0xC000 to 0xC0FF
Controller Register = 1
Actual External ROM 0x8000 to 0xBFFF
Unused Overlay Memory Space 0xC000 to 0xC0FF
Actual External ROM 0xC100 to 0xE7FF ROM (16Kx16)
or
Actual External ROM 0xC100 to 0xE7FF ROM (16Kx16)
or
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4.15
General Timers and Watch Dog Timer
The SL11R Controller has two built in programmable timers that can provide an interrupt to the SL11R Engine. The timers decrement on every microsecond clock tick. An interrupt occurs when the timer reaches zero. 4.15.1 Timer 0 Count Register (0xC010: R/W)
The SL11R BIOS uses the timer 0 for time-out function and power down mode. At the end of the power up, the SL11R BIOS disables the timer 0 interrupt. If you wish to use timer 0 for power down function, see the [Ref. 1] SL11R_BIOS for more information. D15 T15 D14 T14 D13 T13 D12 T12 D11 T11 D10 T10 D9 T9 D8 T8 D7 T7 D6 T6 D5 T5 D4 T4 D3 T3 D2 T2 D1 T1 D0 T0
D15-0 4.15.2
T15-0
Timer Count value.
Timer 1 Count Register (0xC012: R/W)
The SL11R timer 1 is for user applications. The SL11R BIOS does not use this timer. D15 T15 D14 T14 D13 T13 D12 T12 D11 T11 D10 T10 D9 T9 D8 T8 D7 T7 D6 T6 D5 T5 D4 T4 D3 T3 D2 T2 D1 T1 D0 T0
D15-0 4.15.3
T15-0
Timer Count value
Watchdog Timer Count & Control Register (0xC00C: R/W)
The SL11R provides a Watchdog timer to monitor certain activities. The Watchdog timer can also interrupt the SL11R processor. The default value of this register is 0x0000. D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 0 D8 0 D7 0 D6 0 D5 WT D4 TO1 D3 TO0 D2 ENB D1 EP D0 RC
D5 D4-3
WT TO1-0
Watchdog Time-out occurred. Time-out Count: 00 01 10 11 01 milliseconds 04 milliseconds 16 milliseconds 64 milliseconds
D2 D1 D0
EP ENB RC
Enable Permanent WD timer. If set ='1' WD timer is always enabled. Cleared only on Reset. Enable WD Timer operation when ='1'. Reset Count. When set = '1'.
Notes: * You must assert Reset Count (RC), before time-out occurs to avoid Watchdog trigger * The Watchdog Timer overflow causes an internal processor reset. The Processor can read the WT bit after exiting reset to determine if the WT bit is set. If it is set, a watchdog time-out occurred. * The WT value will be cleared on the next external reset.
4.16
Special GPIO Function for Suspend, Resume and Low-Power modes
The SL11R CPU supports suspend, resume and CPU low power modes. The SL11R BIOS assigns GPIO29 for the USB DATA+ line pull-up (This pin can simulate USB cable removal or insertion while USB power is still applied to the circuit) and the GPIO20 Document #: 38-08006 Rev. ** Page 33 of 85
SL11R
for controlling power off function. The GPIO20 can be used for device low power mode; it will remove power from the peripherals in suspend mode. Once USB power is restored, the power to the peripherals may be enabled. The SL11R BIOS will execute the pull up interrupt upon power-up. To use this feature, the GPIO29 pin must be connected to the DATA+ line of the USB connector (see Figure below). For more information about this function, see the [Ref. 1] SL11R_BIOS. GPIO29
1.5 K USB type B Connector 33 33 1 2 3 4 VCC DD+ GND
Figure 4-6. Special GPIO Pull-up Connection Example
4.17
Programmable Pulse/PWM Interface
The SL11R Controller supports four Programmable Digital Pulse output channels. These channels can also be used for Pulse Width Modulation (PWM) operation. Operation is directed by the PWM Control Register, Maximum Count Register, and the individual Start and Stop Counter Registers. These are provided for each of the four output channels. To set up PWM operation, the Maximum Count Register is set to the desired maximum count value. Then the start and stop value for each channel is written with the required values. The start and stop values are chosen to achieve the desired pulse widths during each cycle. When the channels are disabled (by the Control Register), the associated I/O pins revert to GPIO use.
5&/.
6WDUW 3UHVFDOHU
6WRS
&RPSDUH
3:0
ELW &RXQWHU
&RPSDUH 6WDUW 6WRS
3:0
0D[ &RXQW 5HJLVWHU
2QH 6KRW 5 LW
&RPSDUH
3:0
&RPSDUH PWM Block Diagram
3:0
Figure 4-7. PWM Block Diagram Note: The RCLK is the resulting clock (see the Speed Control Register (0xC006: R/W)). 4.17.1 PWM Control Register (0xC0E6: R/W) D15 ST D14 0 D13 0 D12 0 D11 SC2 D10 SC1 D9 SC0 D8 OS D7 P3 D6 P2 D5 P1 D4 P0 D3 EN3 D2 EN2 D1 EN1 D0 EN0 Page 34 of 85
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D15 D14-12 D11-9 SC2-0 000 001 010 011 100 101 110 111 Freq. 48.00 MHz 24.00 MHz 06.00 MHz 01.50 MHz 375 kHz 93.80 kHz 23.40 kHz 05.90 kHz ST Reserved SC2-0 Start Bit. Set to '1' to begin operation. '0' stops operation always '0' 's. Prescaler value selection
D8
OS Enable One Shot Mode for PWM channels. One Shot mode runs the number of counter cycles set in the PWM cycle count register and then stops. The default is continuous repeat.
D7-D4 D3-D0
P3-0 Individual Polarity bits for channels 3 - 0. '1' is active high or rising edge pulse. EN3-0 Individual Enable bits for channels 3 - 0. '1' enables.
Notes: * If not enabled, i.e., if set is '0', the pins become GPIO. To force the outputs to `0' or `1': * If start register = stop register, then output stays at "0" * If stop register > Max count register, then output stays at "1" 4.17.2 PWM Maximum Count Register (0xC0E8: R/W) D15 0 D15-10 D9-0 4.17.3 D14 0 D13 0 D12 0 D11 0 D10 0 D9 C9 D8 C8 D7 C7 D6 C6 D5 C5 D4 C4 D3 C3 D2 C2 D1 C1 D0 C0
Reserved C9-C0
always '0' 's. Maximum Count Value.
PWM Channel 0 Start Register (0xC0EA: R/W) D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 S9 D8 S8 D7 S7 D6 S6 D5 S5 D4 S4 D3 S3 D2 S2 D1 S1 D0 S0
D15-10 D9-0
Reserved S9-S0
always '0' 's. Start Count for PWM Channel 0.
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4.17.4 PWM Channel 0 Stop Register (0xC0EC: R/W) D15 0 D15-10 D9-0 4.17.5 D14 0 D13 0 D12 0 D11 0 D10 0 D9 S9 D8 S8 D7 S7 D6 S6 D5 S5 D4 S4 D3 S3 D2 S2 D1 S1 D0 S0
Reserved S9-S0
always '0' 's. Stop Count for PWM Channel 0.
PWM Channel 1 Start Register (0xC0EE: R/W) D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 S9 D8 S8 D7 S7 D6 S6 D5 S5 D4 S4 D3 S3 D2 S2 D1 S1 D0 S0
D15-10 D9-0 4.17.6
Reserved S9-S0
always '0' 's. Start Count for PWM Channel 1.
PWM Channel 1 Stop Register (0xC0F0: R/W) D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 S9 D8 S8 D7 S7 D6 S6 D5 S5 D4 S4 D3 S3 D2 S2 D1 S1 D0 S0
D15-10 D9-0 4.17.7
Reserved S9-S0
always '0' 's. Stop Count for PWM Channel 1.
PWM Channel 2 Start Register (0xC0F2: R/W) D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 S9 D8 S8 D7 S7 D6 S6 D5 S5 D4 S4 D3 S3 D2 S2 D1 S1 D0 S0
D15-10 D9-0 4.17.8
Reserved S9-S0
always '0' 's. Start Count for PWM Channel 2.
PWM Channel 2 Stop Register (0xC0F4: R/W) D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 S9 D8 S8 D7 S7 D6 S6 D5 S5 D4 S4 D3 S3 D2 S2 D1 S1 D0 S0
D15-10 D9-0 4.17.9
Reserved S9-S0
always '0' 's. Stop Count for PWM Channel 2.
PWM Channel 3 Start Register (0xC0F6: R/W) D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 S9 D8 S8 D7 S7 D6 S6 D5 S5 D4 S4 D3 S3 D2 S2 D1 S1 D0 S0
D15-10 D9-0
Reserved S9-S0
always '0' 's. Start Count for PWM Channel 3. Page 36 of 85
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4.17.10 PWM Channel 3 Stop Register (0xC0F8: R/W) D15 0 D15-10 D9-0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 S9 D8 S8 D7 S7 D6 S6 D5 S5 D4 S4 D3 S3 D2 S2 D1 S1 D0 S0
Reserved S9-S0
always '0' 's. Stop Count for PWM Channel 3.
4.17.11 PWM Cycle Count Register (0xC0FA: R/W) D15 C15 D15-0 D14 C14 D13 C13 D12 C12 D11 C11 D10 C10 D9 C9 D8 C8 D7 C7 D6 C6 D5 C5 D4 C4 D3 C3 D2 C2 D1 C1 D0 C0
C15-0 Number of cycles to run in one-shot mode (0-64K) The OS bit in the PWM Control Register must be set.
Note: Number of OS Cycles to run = C+1. Example for 1 Cycle, set C=2
4.18
Fast DMA Mode
This mode is currently used by the DVC 8-Bit DMA and 8/16-Bit DMA modes. In DVC 8-Bit DMA mode, the DMA data path will be 8, which corresponds to SD7-SD0. In the 8/16-Bit DMA mode, the DMA data path can be configured as either 8 or 16. 4.18.1 DMA Control Register (0xC02A: R/W) D7 0 D6 0 D5 0 D4 0 D3 0 D2 TSZ D1 DIR D0 DMA
External device data presented to S15-SD0/SD7-SD0 is automatically written into the RAM of the SL11R, under fast DMA control. The DMA must be enabled in the DMA Control and Address register. D2 D1 TSZ DIR DMA Direction. When set to '0', data transfers from Peripheral to Memory. When set to '1' Memory to Peripheral. D0 DMA DMA Enabled when set to '1'. Bit clears to `0' when DMA is done. Transfer Size. 8 bit when set to '1', 16-bit when set to '0'
Note for DVC 8-Bit DMA mode: Set Transfer Size to 16 bits for the DVC 8-Bit DMA mode. Set DMA Direction for Peripheral to Memory for DVC 8-Bit DMA mode. 4.18.2 Low DMA Start Address Register (0xC02C: R/W)
This register contains the low order word of the starting DMA address.
D15 A15 D15-0 D14 A14 D13 A13 D12 A12 D11 A11 D10 A10 D9 A9 D8 A8 D7 A7 D6 A6 D5 A5 D4 A4 D3 A3 D2 A2 D1 A1 D0 A0
A15-A0
Low 16 Bits of DMA address
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SL11R
4.18.3 High DMA Start Address Register (0xC02E: R/W)
This register contains the high order word of the starting DMA address. D7 0 D5-D0 Note: A21 = 1 the starting memory address will be in the DRAM. The A21 bit in the High DMA Stop Address register must match this bit. 4.18.4 Low DMA Stop Address Register (0xC030: R/W) A21-A16 D6 0 D5 A21 D4 A20 D3 A19 D2 A18 D1 A17 D0 A16
High Address bits for DMA start address
This register contains the low order word of the stopping SL11R memory address. This is the last DMA address in memory. DMA will stop when this address is reached and if the FDMA bit in the Interrupt Enable Register (0xC00E: R/W) is enabled, an interrupt will also be generated. D15 A15 D15-0 4.18.5 D14 A14 D13 A13 D12 A12 D11 A11 D10 A10 D9 A9 D8 A8 D7 A7 D6 A6 D5 A5 D4 A4 D3 A3 D2 A2 D1 A1 D0 A0
A15-A0
Low 16 Bits of the DMA stop address
High DMA Stop Address Register (0xC032: R/W)
This register contains the high order word of the stopping SL11R memory address. This is the last DMA address in memory. DMA will stop when this address is reached. D7 0 D5-D0 Note: A21 = 1 the stopping memory address will be in the DRAM. The A21 bit must be matched on the High DMA Start Address register. A21-A16 D6 0 D5 A21 D4 A20 D3 A19 D2 A18 D1 A17 D0 A16
High Address bits for DMA stop address.
5.0
SL11R Interface Modes
The SL11R has four modes. They are General Purpose IO mode, Fast EPP mode, 8-bit DMA mode, and 8/16 DMA, Mailbox Protocol ports mode. These modes are shared and can be configured under software control. Note: The UART and 2-wire serial interface IO pins are fixed in all SL11R Interface modes.
5.1
General Purpose IO mode (GPIO)
In GPIO mode, the SL11R has up to 32 general-purpose I/O signals available. However, there are 4 pins used by the UART and the 2-wire serial interface that cannot be used as the GPIO pins. A typical application for this GPIO is Parallel Port to USB. The SL11R executes at 48MHz -- fast enough to generate any Parallel Port timing. The SL11R also includes a special mode for EPP timing designed for special devices that have no delay in the EPP mode. Other available General Purpose I/O pins can be programmed for peripheral control and/or status, etc. When the SL11R interface is in GPIO mode, a number of GPIO pins are used to support the parallel interface. The remaining pins can be used for GPIO or if desired, some can be configured for special functions. The following registers are used for all pins configured as GPIO. The outputs are enabled in the I/0 Control registers. Note that the output Data can be read back via the Output Data Register even if the outputs are not enabled. Note: The Fast DMA and PWM Interface will not be supported in this mode.
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SL11R
5.1.1 I/O Control Register 0 (0xC022: R/W)
This register controls the input/output direction of the GPIO data pins from GPIO15 to GPIO0. When any bit of this register set to one, the corresponding GPIO data pin becomes an output pin. When any bit of this register is set to zero, the corresponding GPIO data pin becomes an input pin. D15 E15 D15-0 5.1.2 D14 E14 D13 E13 D12 E12 D11 E11 D10 E10 D9 E9 D8 E8 D7 E7 D6 E6 D5 E5 D4 E4 D3 E3 D2 E2 D1 E1 D0 E0
E15-0
Enable individual outputs, GPIO 15-0. Logic '1' enables.
I/O Control Register 1 (0xC028: R/W)
This register controls the input/output direction of the GPIO data pins from GPIO31 to GPIO16. When any bit of this register set to one, the corresponding GPIO data pin becomes an output pin. When any bit of this register is set to zero, the corresponding GPIO data pin becomes an input pin. D15 E31 D15-0 5.1.3 D14 E30 D13 E29 D12 E28 D11 E27 D10 E26 D9 E25 D8 E24 D7 E23 D6 E22 D5 E21 D4 E20 D3 E19 D2 E18 D1 E17 D0 E16
E31-16
Enable individual outputs, GPIO 31-16. Logic '1' enables.
Output Data Register 0 (0xC01E: R/W)
This register controls the output data of the GPIO data pins from GPIO15 to GPIO0. Note: A read of this register reads back the last data written, not the data on pins configured as input (see below). D15 O15 D15-0 5.1.4 D14 O14 D13 O13 D12 O12 D11 O11 D10 O10 D9 O9 D8 O8 D7 O7 D6 O6 D5 O5 D4 O4 D3 O3 D2 O2 D1 O1 D0 O0
O15-0
Output Pin Data
Output Data Register 1 (0xC024: R/W)
This register controls the output data of the GPIO data pins from GPIO31 to GPIO16. D15 O31 15 D15-0 5.1.5 D14 O30 14 D13 O29 13 D12 O28 12 D11 O27 11 D10 O26 10 D9 O2 59 D8 O2 48 D7 O2 37 D6 O2 26 D5 O2 15 D4 O2 04 D3 O1 93 D2 O1 82 D1 O1 7 D0 O1 60
O31-16
Output Pin Data
Input Data Register 0 (0xC020: Read only)
This register reads the input data of the GPIO data pins from GPIO15 to GPIO0. D15 I15 D15-0 5.1.6 D14 I14 I15-0 D13 I13 D12 I12 D11 I11 D10 I10 D9 I9 D8 I8 D7 I7 D6 I6 D5 I5 D4 I4 D3 I3 D2 I2 D1 I1 D0 I0
Input Pin data
Input Data Register 1 (0xC026: Read only)
This register reads the input data of the GPIO data pins from GPIO31 to GPIO16.
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D15 I31 D15-0 D14 I30 D13 I29 D12 I28 D11 I27 D10 I26 D9 I25 D8 I24 D7 I23 D6 I22 D5 I21 D4 I20 D3 I19 D2 I18 D1 I17 D0 I16
I31-16
Input Pin data
ENB from I/O Control Register I/O Pin Output Data from Output data Register Read back of Output Data Register Input Data To Input Data Register
Internal I/O Register Data Path
Figure 5-1. GPIO Mode Block Diagram\
5.2
8/16-bit DMA Mode
This mode includes the Mailbox Protocol and DMA Protocol. The Mailbox Protocol allows asynchronous exchange of data between an external Processor (i.e. DSP or Microprocessors) and the SL11R, via the bidirectional data port SD15-SD0 (GPIO15-0). The DMA Protocol allows the large data blocks to be transferred to or from SL11R memory devices via the 8/16-bit DMA port. The SL11R has four built-in PWM output channels available in the 8/16-bit DMA mode. Each channel provides a programmable timing generator sequence which can be used to interface to various line CCD, CIS, CMOS image sensors or can be used for other types of applications (see Programmable Pulse/PWM Interface for more detail of controlling these PWM functions). Note: Any other unused IO pins can be used as the GPIO pins under control of the General Purpose IO mode (GPIO).
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SL11R
SD15-0 INBUFF
DAADrA '
OUTBUFF STATUS
SL11R PROCESSOR
PAADrA &
9H6Aissr
DATA15-0
Q&6 Q:5,7( Q5($' '5(4 $''5
Figure 5-2. 8/16-bit DMA Mode Block Diagram 5.2.1 Mailbox Protocol
The physical interface for the Mailbox is shared with the DMA data path on the SD15-SD0 bus. When accessing the Mailbox INBUFF & OUTBUFF registers, the ADDR pin should be driven high. The ADDR pin should be driven low to access the Mailbox STATUS register. The external processor and SL11R can both access the INBUFF, OUTBUFF & STATUS Mailbox registers. The SL11R includes two interrupt vectors for this Mailbox Protocol. Whenever the external Processor accesses the Mailbox, the associated interrupt will be generated. Note: * To enable the Mailbox interrupt, the bit MBX in the Register 0xC00E must be enabled. * The external processor cannot access the Mailbox while DMA is in progress. 5.2.2 INBUFF Data Register (0xC0C4: R/W)
The external processor will write to this register with the ADDR signal set to one and the SL11R will read this register after receiving the interrupt (if the MBX interrupt is enabled in the Register 0xC00E). D15 D15 D15-0 5.2.3 D14 D14 D13 D13 D12 D12 D11 D11 D10 D10 D9 D9 D8 D8 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0
D15-0
Data from input Mailbox
OUTBUFF Data Register (0xC0C4: R/W)
The SL11R will write to this register and the external processor will read from this register with the ADDR signal set to one. The SL11R will receive an interrupt after the external processor finished reading (if the MBX interrupt is enabled in the Register 0xC00E). D15 D15 D15-0 D14 D14 D13 D13 D12 D12 D11 D11 D10 D10 D9 D9 D8 D8 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0
D15-0
Data for Output Mailbox Page 41 of 85
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5.2.4 STATUS Register (0xC0C2: Read Only)
The external processor can read the STATUS of the OUTBUFF and INBUFF Status bits from this output buffer. The external ADDR pin should be driven to low when reading this STATUS register. D15 0 D1 D0 Note: The SL11R also can access this register. 5.2.5 DMA Protocol D14 0 IF OF D13 0 D12 0 D11 0 D10 0 D9 0 D8 0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 IF D0 OF
INBUFF Full OUTBUFF Full
The physical interface for the DMA is shared with the Mailbox protocol on the SD15-SD0 bus. If the DREQ (DMA Request Enable) bit is set, this enables SL11R DMA cycles to or from the external device (scanner, printer, camera, modem or etc.). The DREQ is asserted by the SL11R when data is ready to be sent or received. When the external device is ready to send Data, it asserts the nWRITE signal. Data must be available at this point. If the external device is ready to accept data, it asserts the nREAD signal. The DMA mode can be used to move large amounts of data to or from a variety of peripherals such as Scanners, Printers, Cable Modems, External Storage devices, and others. For example for a DVC, video data from the camera can be moved via DMA to an internal memory buffer for subsequent transfer to the USB host. This data can be transferred to the host via the USB DMA engine (i.e. no SL11R Processing is involved, since the USB has its own DMA engine). Users can program 8 bit or 16 bit DMA transfers in either direction; Peripheral to SL11R or SL11R to Peripheral. A control register (0xC02A) sets the DMA bus width, direction and DMA enable and four further registers control the DMA start and end addresses (see Fast DMA Mode, section 2.14). Furthermore, if the FDMA bit in Register 0xC00E is enabled, an interrupt will be issued to indicate the DMA operation is complete. 5.2.6 DMA Control Register (0xC0C0: R/W)
Before setting this register, the Low DMA Start Address (0xC02C), High DMA Start Address (0xC02E), the Low DMA Stop Address (0xC030) and the High DMA Stop Address (0xC032) must be configured. D15 0 D2 D14 0 D13 0 DREQ External DREQ DMA Enable, if set to `1', the SL11R can DMA to or from the external device (scanner or printer) by asserting the DREQ signal when data is requested or ready to send. D1 D0 D1 D0 Set to `1' Set to `1' D12 0 D11 0 D10 0 D9 0 D8 0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 DREQ D1 D1 D0 D0
5.3
Fast EPP Mode
This interface is designed to interface with a specially optimized high-speed EPP interface. The SL11R processor has direct access to the EPP control port. The EPP function has four transfer modes: Data Write, Data Read, Address Write and Address Read. Strobe signals nDTSRB and nASTRB are generated by the SL11R for data or address operations respectively. The signal nWRITE indicates read or write as described below. Note: * The Fast DMA and PWM Interface will not be supported in this mode. * Any other unused IO pins can be used as the GPIO pins under control of theGeneral Purpose IO mode (GPIO).
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SL11R
5.3.1 EPP Data Register (0xC040: R/W)
Writing to this register results in the generation of a pulse on the nDTSRB output pin, with the nWRITE output pin low, and the register data being driven onto the SD7-SD0 Data bus. Reading from this register results in the generation of a pulse on the nDTSRB output pin, with the nWRITE output pin high, and data being read from the SD7-SD0 Data bus. D7 SD7 D7-D0 5.3.2 D6 SD6 SD7-SD0 D5 SD5 EPP data D4 SD4 D3 SD3 D2 SD2 D1 SD1 D0 SD0
EPP Address Register (0xC044: R/W)
Writing to this register results in the generation of a pulse on the nASTRB output pin, with the nWRITE output pin low, and the register data being driven onto the SD7-SD0 Data bus. Reading from this register results in the generation of a pulse on the nASTRB output pin, with the nWRITE output pin high, and data being read from the SD7-SD0 Data bus. D7 A7 D7-D0 5.3.3 D6 A6 A7-A0 D5 A5 D4 A4 D3 A3 D2 A2 D1 A1 D0 A0
Device and register address value from the SD7-SD0 Data Bus.
EPP Address Buffer Read Register (0xC046: Read Only)
Reading this register returns existing data from Read Buffer to the I/O processor. The nASTRB will not be asserted. D7 A7 D7-D0 5.3.4 D6 A6 A7-A0 D5 A5 Read Data D4 A4 D3 A3 D2 A2 D1 A1 D0 A0
EPP Data Buffer Read Register (0xC042: Read Only)
Reading this register returns existing data from Read Buffer to the I/O processor. The nDTSRB will not be asserted D7 SD7 D7-D0 5.3.5 D6 SD6 SD7-SD0 D5 SD5 D4 SD4 D3 SD3 D2 SD2 D1 SD1 D0 SD0
EPP data from the SD7-SD0 data bus.
EPP Status Data Register (0xC04E: R/W)
This register is used to read the actual status signal from GPIO9-8. The P9 pin will be set to the value in D7 when written. GPIO8 and GPIO9 are not affected by writing to this register. D7 P9 (GPIO21) D7 D1 D0 P9 INTR WAIT D6 0 D5 0 D4 0 D3 0 D2 0 D1 INTR D0 WAIT
Value output on GPIO21. from the GPIO8 line from GPIO9. Page 43 of 85
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5.3.6 EPP P_REG Register (0xC050: R/W)
The SL11R has a set of eight pins labeled P1-P8, which are general-purpose output pins. The functionality of each bit is selected in the respective Control Register. The SL11R 16-bit processor has access to these pins through a read write, which is defined in the P_REG register. The bit assignments are noted in the following table. D7 P8 (GPIO15) D7-D0 Note: A write to this register causes the SL11R to write this out the corresponding GPIO pins (Except P6). The output value of the P6 will be the complement of the value written. 5.3.7 Serial Interface Registers D6 P7 (GPIO14) P8-P1 D5 P6 (!GPIO13) D4 P5 (GPIO20) D3 P4 (GPIO19) D2 P3 (GPIO18) D1 P2 (GPIO17) D0 P1 (GPIO16)
Set to logic `1' or `0' for corresponding P output pin
The SL11R supports subset of an industry standard SPI serial interface, which provides the interface to serial interface device like Multi-Media or Memory Stick interface. 5.3.7.1 Serial Interface Control & Status Register Address C048H
The Serial Interface port of the SL11R can be used to control certain aspects of the interface to serial Memory Flash devices. There are cycles (Address, Write or Read) are implemented on this mode. D7 0 D7-1 D0 D6 0 Not Defined. B - Busy. When Set = '1', indicates a cycle is in progress. Cleared to '0' when the cycle has completed. No new cycles are allowed until Busy bit = '0'. 5.3.7.2 Serial Interface Address Register D7 A7 D6 A6 D5 A5 D4 A4 Address C04AH D3 A3 D2 A2 D1 A1 D0 A0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 B
A7-A0: Address value. Writing a value to this register results in an address cycle on the serial bus. The Busy bit in the status register (C048H) goes to '1' (high) until cycle has completed. 5.3.7.3 Serial Interface Data Write Register D7 TD7 D6 TD6 D5 TD5 D4 TD4 Address C04CH D3 TD3 D2 TD2 D1 TD1 D0 TD0
TD7-0: Data to be transmitted. Writing to this register initiates a write cycle on the serial data bus. The busy bit in the status register (C048H) goes to '1' (high) until the cycle has completed.
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SL11R
5.3.7.4 Serial Interface Data Read Register D7 RD7 D6 RD6 D5 RD5 D4 RD4 Read OnlyAddress C04CH D3 RD3 D2 RD2 D1 RD1 D0 RD0
RD7-0: Read Data. Reading this register initiates a read cycle on the serial bus and sets the Busy bit = '1' in the Status Register (C048H). Read data is valid when the Busy bit in the status register is cleared to '0'. Notes: The clock rate for the serial operation is 12MHz base on the processor clock at 48MHz. To change the clock rate user can change the processor clock rate via the register C008H. A delay is needed between back to back serial accesses to allow serial shifting to occur. GPIO11 will be used as the DATAS. GPIO26 will be used as the CLKS. GPIO25 will be used as the nENS (Can use this as the interrupt IRQ1). The register C006H need to select this mode to make the interface work.
5.4
DVC 8-bit DMA Mode
This mode is designed to interface with CCD cameras. Camera control and setup is performed through the serial control bus. The SL11R 16-bit processor has direct access to the control port and the camera operation is dependent on commands passed from the USB Host to the SL11R. Raw video data from the Camera is input to the SL11R on the 8-bit video data bus (SD7-SD0) using a combination of clock and control signals and 8 bit DMA. The signals include a clock (MCK0), Field Index (FI), Sync and blanking signals (SYNC, PBLK), and Drive signals (VD and HD). The DMA Engine is used to transfer the image from the 8-bit bus (SD7-SD0) to external DRAM port. The software uses the Fast DMA configuration registers. Note: * The PWM Interface is not supported in this mode. * Any other unused IO pins can be used as GPIO pins under control of the GPIO mode. 5.4.1 Video Status Register(0xC06E: Read Only)
The camera sends an 8 bit data bus with a number of control signals. The SL11R uses the following control signals to acquire the video data: MCK0 FI VD PBLK SD7-SD0 N_RST From Camera From Camera From Camera From Camera From Camera To Camera Pixel Clock = 9.534965MHz Field Index. Contains 1 Vertical sweep + Blank Active During Vertical Sweep. Active during Horizontal sweep. CCD Video data. Active Low Reset
The first 8 bytes of Data is discarded from the video stream starting at the assertion of each PBLK. After PBLK is de-asserted, 7 more bytes of data are taken. The Video Control and Status Register allows the acquisition of video images and provides power and reset controls for the camera. D7 0 D7-5 D4 D3 D2 D6 0 Reserved VRST P-CONT Reserved D5 0 Always = '0' Video Reset. '0' Resets Camera (See Note). When set = '1' powers up camera. Always = '0'. Page 45 of 85 D4 VRST D3 P-CONT D2 0 D1 F D0 SC
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D1 D0 Note: After P-CONT is set high to provide camera power, the Video Reset must be held low a minimum of 100 milliseconds. 5.4.2 Camera Serial Interface Registers F When set = '1' capture even then odd field else when '0' capture even field only. SC Start Capture When set = '1', clears to '0' when done.
The Serial Interface port of the SL11R is used to pass control information to the camera and to communicate with serial EPROM1, and EPROM2 (EPROM 1 is used to store camera default data). The Serial Port Control Register determines if the next operation will be a write cycle to the camera or the EEPROM, or if the operation will be a read cycle of the EPROM. When an EPROM or camera cycle is required the device must be selected in the Control Register, and an EEPROM address location must be written to the Serial Interface Address Register. When a Read Cycle is selected, writing the Busy Bit begins the cycle, and when completed, the valid returned data can be read in the Serial Interface Data Read Register. The SL11R has a dedicated serial bus to support the camera and EPROM. On power up, an SL11R signal, AEEP, is driven high, (AEEP connects to the Camera DSP device), the SL11R Camera serial bus is three-stated, which allows the Camera DSP to read the camera default data directly from the EEPROM. (During this time the DSP drives the Serial Clock to the EEPROM and the CCS select line to the SL11R, EEP1 is driven high from the SL11R). After a timed interval, the AEEP line is driven low and the SL11R can now communicate to the camera via the Camera Serial Port. 5.4.3 Serial Interface Control & Status Register (0xC068: R/W) D7 0 D7-3 D2-D1 Reserved M1-M0 D6 0 0 Mode Setting: 11 = AEEP MODE 10 = EPROM 2 01 = EPROM1 00 = DSP PROCESSOR D0 Busy When Set = '1', initiates a cycle to selected target. Cleared to '0' when the cycle has completed. No new cycles are allowed until Busy bit = '0'. 5.4.4 Serial Interface Address Register (0xC06A: Write Only) D8 P2 D8-6 D5-0 5.4.5 P2- P0 A5-A0 D7 P1 D6 P0 D5 A5 D4 A4 D3 A3 D2 A2 D1 A1 D0 A0 D5 0 D4 0 D3 0 D2 M1 D1 M0 D0 Busy
Command: 101 = Write, 110 = read EEPROM or Camera Register address.
Serial Interface Data Write Register (0xC06C: Write Only)
When data is transmitted, setting the Busy bit in the Control Status Register initiates transmission. D15 T15 D15-0 D14 T14 D13 T13 D12 T12 D11 T11 D10 T10 D9 T9 D8 T8 D7 T7 D6 T6 D5 T5 D4 T4 D3 T3 D2 T2 D1 T1 D0 T0
T15-0
Data to be transmitted.
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SL11R
5.4.6 Serial Interface Data Read Register (0xC06C: Read Only)
Read cycle data from the selected device in Control Status Register, and address specified in the Address Register. Data is valid after a Read Cycle has been initiated by setting the Busy bit in the Status Register. Data is valid after Busy bit clears to '0'. D15 R15 D15-0 D14 R14 D13 R13 D12 R12 D11 R11 D10 R10 D9 R9 D8 R8 D7 R7 D6 R6 D5 R5 D4 R4 D3 R3 D2 R2 D1 R1 D0 R0
R15-0
Read Data from the SD7-SD0 Data Bus.
5.4.7 I/O Address Map I/O Address Map Function Address Mode
USB Endpoint 0 Address Register USB Endpoint 0 Count Register USB Endpoint 1 Address Register USB Endpoint 1 Count Register USB Endpoint 2 Address Register USB Endpoint 2 Count Register USB Endpoint 3 Address Register USB Endpoint 3 Count Register Configuration Register Speed Control Register Power Down Control Register Watchdog Timer Count & Control Register Interrupt Enable Register Timer 0 Count Register Timer 1 Count Register Breakpoint Register Extended Page 1 Map Register Extended Page 2 Map Register GPIO Interrupt Control Register Output Data Register 0 Input Data Register 0 I/O Control Register 0 Output Data Register 1 Input Data Register 1 I/O Control Register 1 DMA Control Register Low DMA Start Address Register High DMA Start Address Register
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0x0120 0x0122 0x0124 0x0126 0x0128 0x012A 0x012C 0x012E 0xC006 0xC008 0xC00A 0xC00C 0xC00E 0xC010 0xC012 0xC014 0xC018 0xC01A 0xC01C 0xC01E 0xC020 0xC022 0xC024 0xC026 0xC028 0xC02A 0xC02C 0xC02E
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Read Only R/W R/W Read Only R/W R/W R/W R/W
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I/O Address Map (continued) Function Address Mode
Low DMA Stop Address Register High DMA Stop Address Register DRAM Control Register Extended Memory Control Register Memory Control Register EPP Data Register EPP Data Buffer Read Register EPP Address Register EPP Address Buffer Read Register EPP Status Data Register EPP P_REG Register Serial Interface Control & Status Register Serial Interface Address Register Serial Interface Data Write Register Serial Interface Data Read Register Video Status Register USB Global Control & Status Register USB Frame Number Register USB Address Register USB Command Done Register USB Endpoint 0 Control & Status Register USB Endpoint 1 Control & Status Register USB Endpoint 2 Control & Status Register USB Endpoint 3 Control & Status Register DMA Control Register STATUS Register INBUFF Data Register OUTBUFF Data Register UART Control Register UART Status Register UART Transmit Data Register UART Receive Data Register PWM Control Register PWM Maximum Count Register PWM Channel 0 Start Register PWM Channel 0 Stop Register
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0xC030 0xC032 0xC038 0xC03A 0xC03E 0xC040 0xC042 0xC044 0xC046 0xC04E 0xC050 0xC068 0xC06A 0xC06C 0xC06C 0xC06E 0xC080 0xC082 0xC084 0xC086 0xC090 0xC092 0xC094 0xC096 0xC0C0 0xC0C2 0xC0C4 0xC0C4 0xC0E0 0xC0E2 0xC0E4 0xC0E4 0xC0E6 0xC0E8 0xC0EA 0xC0EC
R/W R/W R/W R/W R/W R/W Read Only R/W Read Only R/W R/W R/W Write Only Write Only Read Only Read Only R/W Read Only R/W Write Only R/W R/W R/W R/W R/W Read Only R/W R/W R/W Read Only Write Only Read Only R/W R/W R/W R/W
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SL11R
I/O Address Map (continued) Function Address Mode
PWM Channel 1 Start Register PWM Channel 1 Stop Register PWM Channel 2 Start Register PWM Channel 2 Stop Register PWM Channel 3 Start Register PWM Channel 3 Stop Register PWM Cycle Count Register
0xC0EE 0xC0F0 0xC0F2 0xC0F4 0xC0F6 0xC0F8 0xC0FA
R/W R/W R/W R/W R/W R/W R/W
6.0
6.1
Physical Connection
Package Type
100 PQFP.
6.2
GPIO and 8/16-Bit DMA Modes--Pin Assignment and Description
GPIO and 8/16-Bit DMA Modes--Pin Assignment and Description Pin Name VDD D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 GND X1 X2 VDD D12 D13 D14 D15 A20 A19 A18 Pin No. GPIO Pins Pin Type 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Power Bidir Bidir Bidir Bidir Bidir Bidir Bidir Bidir Bidir Bidir Bidir Bidir GND Input Output Power Bidir Bidir Bidir Bidir Output Output Output GPIO & 8/16-bit DMA modes Pin Chip Revision 1.1 +3.3 VDC Supply External Memory Data Bus, Data0 External Memory Data Bus, Data1 External Memory Data Bus, Data2 External Memory Data Bus, Data3 External Memory Data Bus, Data4 External Memory Data Bus, Data5 External Memory Data Bus, Data6 External Memory Data Bus, Data7 External Memory Data Bus, Data8 External Memory Data Bus, Data9 External Memory Data Bus, Data10 External Memory Data Bus, Data11 Digital ground. External 48-MHz Crystal or Clock Input. External crystal output. No connection when X1 is used for clock input +3.3 VDC Supply External Memory Data Bus, Data12 External Memory Data Bus, Data13 External Memory Data Bus, Data14 External Memory Data Bus, Data15 External Memory Address Bus, A20 External Memory Address Bus, A19 External Memory Address Bus, A18 Page 49 of 85
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GPIO and 8/16-Bit DMA Modes--Pin Assignment and Description (continued) Pin Name A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 GND A2 A1 A0 TEST nWRL nWRH nRD nRESET nRAS VDD VDD nCASL nCASH nDRAMOE nDRAMWR nXRAMSEL nXROMSEL nXMEMSEL X_PCLK SECLK SEDO USB_PU UART_TXD Pin No. GPIO Pins Pin Type 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 GPIO31 GPIO30 GPIO29 GPIO28 Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output GND Output Output Output Input Output Output Output Input Output Power Power Output Output Output Output Output Output Output Bidir Bidir Bidir Bidir Output GPIO & 8/16-bit DMA modes Pin Chip Revision 1.1 External Memory Address Bus, A17 External Memory Address Bus, A16 External Memory Address Bus, A15 External Memory Address Bus, A14 External Memory Address Bus, A13 External Memory Address Bus, A12 External Memory Address Bus, A11 External Memory Address Bus, A10 External Memory Address Bus, A9 External Memory Address Bus, A8 External Memory Address Bus, A7 External Memory Address Bus, A6 External Memory Address Bus, A5 External Memory Address Bus, A4 External Memory Address Bus, A3 Digital ground. External Memory Address Bus, A2 External Memory Address Bus, A1 External Memory Address Bus, A0 No Connection, MFG test only Note: SL11RB NC=48 MHz, GND=12 MHz Active LOW, write to lower bank of External SRAM Active LOW, Write to upper bank of External SRAM Active LOW, Read from External SRAM or ROM Master Reset. SL11R Device active LOW reset input. Active low, DRAM Row Address Select +3.3 VDC Supply +3.3 VDC Supply Active LOW, DRAM Column Low Address Select Active LOW, DRAM Column High Address Select Active LOW, DRAM Output Enable Active LOW, DRAM Write Active LOW, select external SRAM (16 bit) Active LOW, select external ROM Active LOW, select external Memory bus, external SRAM, DRAM, ROM or any memory mapped device See register 0xC006 for more information SECLK, Serial EEPROM clock, or GPIO31 SEDO, Serial flash EPROM Data, or GPIO30 This pin requires a 5-k pull-up. Turn on/off D+ Pull Up Resistor, or GPIO29 UART Transmit Data (out), or GPIO28 Page 50 of 85
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GPIO and 8/16-Bit DMA Modes--Pin Assignment and Description (continued) Pin Name GND GND UART_RXD PWR_OFF Pin No. GPIO Pins Pin Type 64 65 66 67 GPIO27 GPIO26 GND GND Input Bidir GPIO & 8/16-bit DMA modes Pin Chip Revision 1.1 Digital ground. Digital ground. UART Receive Data (in), or GPIO27 This signal can be used for device low-power mode, it will turn off or disable external powers to the peripheral in suspend mode. Once USB power is resumed, external power can be enabled again GPIO25, or IRQ1 (in) interrupts the SL11R processor IRQ0 (in) interrupts the SL11R processor or PWM. See the PWM Control register set-up for more information Same as above or GPIO23 Same as above or GPIO22 Same as above or GPIO21 DMA Request Enable. DREQ indicates that SL11R is ready to accept or send data from/to an external device. DREQ along with nCS, nWRITE and nREAD bits are the DMA handshake signals for the main SDATA port, or GPIO20. ADDR =1, Read/Write data from the INBUF/OUTBUFF, ADDR=0 read data from the STATUS register, or GPIO19 +3.3 VDC Supply CS (in) Active LOW, Selects the bidirectional SDATA Port, or GPIO18 Active input LOW signal used to indicate write data transfers to the general bidirectional SD15-0 Data Port. Signal is driven high for read transfers to the SL11R, or GPIO17 Active LOW input signal used to indicate read data transfers from the general bidirectional SD15-0 Data Port. Or GPIO16 Digital ground. Main bidirectional SDATA port bit 15, or GPIO15 Main bidirectional SDATA port bit 14, or GPIO14 Main bidirectional SDATA port bit 13, or GPIO13 Main bidirectional SDATA port bit 12, or GPIO12 Main bidirectional SDATA port bit 11, or GPIO11 Main bidirectional SDATA port bit 10, or GPIO10 Main bidirectional SDATA port bit 9, or GPIO9 USB +3.3 VDC Supply. USB Differential DATA Signal High Side. USB Differential DATA Signal Low Side. USB Digital Ground. Main bidirectional SDATA port bit 8, or GPIO8 Main bidirectional SDATA port bit 7, or GPIO7 Main bidirectional SDATA port bit 6, or GPIO6 Main bidirectional SDATA port bit 5, or GPIO5 Main bidirectional SDATA port bit 4, or GPIO4 Main bidirectional SDATA port bit 3, or GPIO3 Main bidirectional SDATA port bit 2, or GPIO2 Main bidirectional SDATA port bit 1, or GPIO1 Page 51 of 85
IRQ1 (in) PWM3, or IRQ0 (in) PWM2 PWM1 PWM0 DREQ
68 69 70 71 72 73
GPIO25 GPIO24 GPIO23 GPIO22 GPIO21 GPIO20
Bidir Bidir Bidir Bidir Bidir Bidir
ADDR VDD nCS nWRITE
74 75 76 77
GPIO19
Bidir Power
GPIO18 GPIO17
Bidir Bidir
nREAD GND SD15 SD14 SD13 SD12 SD11 SD10 SD9 VDD1 DATA+ DATAGND1 SD8 SD7 SD6 SD5 SD4 SD3 SD2 SD1
78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98
GPIO16
Bidir GND
GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9
Bidir Bidir Bidir Bidir Bidir Bidir Bidir Power Bidir Bidir GND
GPIO8 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1
Bidir Bidir Bidir Bidir Bidir Bidir Bidir Bidir
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GPIO and 8/16-Bit DMA Modes--Pin Assignment and Description (continued) Pin Name SD0 VDD Pin No. GPIO Pins Pin Type 99 100 GPIO0 Bidir Power GPIO & 8/16-bit DMA modes Pin Chip Revision 1.1 Main bidirectional SDATA port bit 0, or GPIO0 +3.3 VDC Supply
6.3
Fast EPP Pin Assignment and Description
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 GPIO pins Pin Type Power Bidir Bidir Bidir Bidir Bidir Bidir Bidir Bidir Bidir Bidir Bidir Bidir GND Input Output Power Bidir Bidir Bidir Bidir Output Output Output Output Output Output Output Output Output Output Output Output Output Output GPIO & Fast EPP Pin Chip Revision 1.1 +3.3 VDC Supply External Memory Data Bus, Data0 External Memory Data Bus, Data1 External Memory Data Bus, Data2 External Memory Data Bus, Data3 External Memory Data Bus, Data4 External Memory Data Bus, Data5 External Memory Data Bus, Data6 External Memory Data Bus, Data7 External Memory Data Bus, Data8 External Memory Data Bus, Data9 External Memory Data Bus, Data10 External Memory Data Bus, Data11 Digital ground. External 48-MHz Crystal or Clock Input. External crystal output. No connection when X1 is used for clock input +3.3 VDC Supply External Memory Data Bus, Data12 External Memory Data Bus, Data13 External Memory Data Bus, Data14 External Memory Data Bus, Data15 External Memory Address Bus, A20 External Memory Address Bus, A19 External Memory Address Bus, A18 External Memory Address Bus, A17 External Memory Address Bus, A16 External Memory Address Bus, A15 External Memory Address Bus, A14 External Memory Address Bus, A13 External Memory Address Bus, A12 External Memory Address Bus, A11 External Memory Address Bus, A10 External Memory Address Bus, A9 External Memory Address Bus, A8 External Memory Address Bus, A7 Page 52 of 85
Fast EPP Pin Assignment and Description Pin Name VDD D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 GND X1 X2 VDD D12 D13 D14 D15 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7
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Fast EPP Pin Assignment and Description (continued) Pin Name A6 A5 A4 A3 GND A2 A1 A0 TEST nWRL nWRH nRD nRESET nRAS VDD VDD nCASL nCASH nDRAMOE nDRAMWR nXRAMSEL nXROMSEL nXMEMSEL X_PCLK SECLK SEDO GPIO29 UART_TXD GND GND UART_RXD nENS CLKS nDTSRB nASTRB nWRITE P9 P5 P4 Pin No. 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 GPIO27 GPIO26 GPIO25 GPIO24 GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO31 GPIO30 GPIO29 GPIO28 GPIO pins Pin Type Output Output Output Output GND Output Output Output Input Output Output Output Input Output Power Power Output Output Output Output Output Output Output Bidir Bidir Bidir Bidir Output GND GND Input Output Output Output Output Output Output Output Output GPIO & Fast EPP Pin Chip Revision 1.1 External Memory Address Bus, A6 External Memory Address Bus, A5 External Memory Address Bus, A4 External Memory Address Bus, A3 Digital ground. External Memory Address Bus, A2 External Memory Address Bus, A1 External Memory Address Bus, A0 No Connection, MFG test only Active LOW, write to lower bank of External SRAM Active LOW, Write to upper bank of External SRAM Active LOW, Read from External SRAM or ROM Master Reset. SL11R Device active low reset input. Active low, DRAM Row Address Select +3.3 VDC Supply +3.3 VDC Supply Active LOW, DRAM Column Low Address Select Active LOW, DRAM Column High Address Select Active LOW, DRAM Output Enable Active LOW, DRAM Write Active LOW, select external SRAM (16 bit) Active LOW, select external ROM Active LOW, select external Memory bus, external SRAM, DRAM, ROM or any memory mapped device See register 0xC006 for more information SECLK, Serial EEPROM clock, or GPIO31 SEDO, Serial flash EPROM Data, or GPIO30 This pin requires a 5K Ohm pull-up. GPIO29 UART Transmit Data (out), or GPIO28 Digital ground. Digital ground. UART Receive Data (in), or GPIO27 Serial EPROM control signal Serial EPROM Clock EPP Data Strobe EPP Address Strobe EPP Write Strobe P Register P Register or PWR_OFF P Register
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Fast EPP Pin Assignment and Description (continued) Pin Name VDD P3 P2 P1 GND P6 P7 P8 GPIO12 DATAS VREQ WAIT VDD1 DATA+ DATAGND1 INTR SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 VDD Pin No. 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 GPIO8 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO18 GPIO17 GPIO16 GPIO pins Pin Type Power Output Output Output GND Output Output Output Bidir Bidir Input Bidir Power Bidir Bidir GND Input Bidir Bidir Bidir Bidir Bidir Bidir Bidir Bidir Power GPIO & Fast EPP Pin Chip Revision 1.1 +3.3 VDC Supply P Register or USB_PU (USB DATA+ pull up) P Register P Register Digital ground. P Register P Register P Register GPIO12 DATA Strobe for Serial EPROM TBD EPP WAIT signal USB +3.3 VDC Supply. USB Differential DATA Signal High Side. USB Differential DATA Signal Low Side. USB Digital Ground. EPP INTR pin EPP Data bit 7 EPP Data bit 6 EPP Data bit 5 EPP Data bit 4 EPP Data bit 3 EPP Data bit 2 EPP Data bit 1 EPP Data bit 0 +3.3 VDC Supply
6.4
DVC 8-Bit DMA Mode Pin Assignment and Description
DVC 8-Bit DMA Mode Pin Assignment and Description Pin Name VDD D0 D1 D2 D3 D4 D5 D6 D7 D8 Pin No. 1 2 3 4 5 6 7 8 9 10 GPIO pins Pin Type Power Bidir Bidir Bidir Bidir Bidir Bidir Bidir Bidir Bidir GPIO & DVC 8-bit DMA modes Pin Chip Revision 1.1 +3.3 VDC Supply External Memory Data Bus, Data0 External Memory Data Bus, Data1 External Memory Data Bus, Data2 External Memory Data Bus, Data3 External Memory Data Bus, Data4 External Memory Data Bus, Data5 External Memory Data Bus, Data6 External Memory Data Bus, Data7 External Memory Data Bus, Data8
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DVC 8-Bit DMA Mode Pin Assignment and Description (continued) Pin Name D9 D10 D11 GND X1 X2 VDD D12 D13 D14 D15 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 GND A2 A1 A0 TEST nWRL nWRH nRD nRESET nRAS VDD VDD Pin No. 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 GPIO pins Pin Type Bidir Bidir Bidir GND Input Output Power Bidir Bidir Bidir Bidir Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output GND Output Output Output Input Output Output Output Input Output Power Power GPIO & DVC 8-bit DMA modes Pin Chip Revision 1.1 External Memory Data Bus, Data9 External Memory Data Bus, Data10 External Memory Data Bus, Data11 Digital ground. External 48-MHz Crystal or Clock Input. External crystal output. No connection when X1 is used for clock input +3.3 VDC Supply External Memory Data Bus, Data12 External Memory Data Bus, Data13 External Memory Data Bus, Data14 External Memory Data Bus, Data15 External Memory Address Bus, A20 External Memory Address Bus, A19 External Memory Address Bus, A18 External Memory Address Bus, A17 External Memory Address Bus, A16 External Memory Address Bus, A15 External Memory Address Bus, A14 External Memory Address Bus, A13 External Memory Address Bus, A12 External Memory Address Bus, A11 External Memory Address Bus, A10 External Memory Address Bus, A9 External Memory Address Bus, A8 External Memory Address Bus, A7 External Memory Address Bus, A6 External Memory Address Bus, A5 External Memory Address Bus, A4 External Memory Address Bus, A3 Digital ground. External Memory Address Bus, A2 External Memory Address Bus, A1 External Memory Address Bus, A0 No Connection, MFG test only Active LOW, write to lower bank of External SRAM Active LOW, Write to upper bank of External SRAM Active LOW, Read from External SRAM or ROM Master Reset. SL11R Device active low reset input. Active LOW, DRAM Row Address Select +3.3 VDC Supply +3.3 VDC Supply Page 55 of 85
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DVC 8-Bit DMA Mode Pin Assignment and Description (continued) Pin Name nCASL nCASH nDRAMOE nDRAMWR nXRAMSEL nXROMSEL nXMEMSEL X_PCLK SECLK SEDO GPIO29 UART_TXD GND GND UART_RXD GPIO26 IRQ1 (in) IRQ0 (in) GPIO23 GPIO22 nVID_RST P_CONT AGC_C VDD AEEP DSP_CS EEP2_CS GND EEP1_CS DO SK PBLK VD FI MCK0 VDD1 DATA+ DATAGND1 Pin No. 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO18 GPIO17 GPIO16 GPIO27 GPIO26 GPIO25 GPIO24 GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO31 GPIO30 GPIO29 GPIO28 GPIO pins Pin Type Output Output Output Output Output Output Output Bidir Bidir Bidir Bidir Output GND GND Input Bidir Bidir Bidir Bidir Bidir Output Output Output Power Output Output Bidir GND Output Output Input Input Input Input Bidir Power Bidir Bidir GND GPIO & DVC 8-bit DMA modes Pin Chip Revision 1.1 Active LOW, DRAM Column Low Address Select Active LOW, DRAM Column High Address Select Active LOW, DRAM Output Enable Active LOW, DRAM Write Active LOW, select external SRAM (16 bit) Active LOW, select external ROM Active LOW, select external Memory bus, external SRAM, DRAM, ROM or any memory mapped device See register 0xC006 for more information SECLK, Serial EEPROM clock, or GPIO31 SEDO, Serial flash EPROM Data, or GPIO30 This pin requires a 5K Ohm pull-up. GPIO29 UART Transmit Data (out), or GPIO28 Digital ground. Digital ground. UART Receive Data (in), or GPIO27 GPIO26 GPIO25, or IRQ1 (in) interrupts the SL11R processor IRQ0 (in) interrupts the SL11R processor or GPIO24 GPIO23 GPIO22 VIDEO Reset Pin P_CONT pin AGC_C control pin +3.3 VDC Supply AEPP pin DSP Chip select pin Serial EPROM2 chip select Digital ground. Serial EPROM1 chip select Serial EPROM Data out pin Serial EPROM Clock pin PBLK from CCD VD from CCD FI from CCD MCK0 from CCD USB +3.3 VDC Supply. USB Differential DATA Signal High Side. USB Differential DATA Signal Low Side. USB Digital Ground.
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DVC 8-Bit DMA Mode Pin Assignment and Description (continued) Pin Name DI SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 VDD Pin No. 91 92 93 94 95 96 97 98 99 100 GPIO pins GPIO8 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 Pin Type Bidir Input Input Input Input Input Input Input Input Power GPIO & DVC 8-bit DMA modes Pin Chip Revision 1.1 Serial EPROM Data Input SDATA port bit 7, or GPIO7 SDATA port bit 6, or GPIO6 SDATA port bit 5, or GPIO5 SDATA port bit 4, or GPIO4 SDATA port bit 3, or GPIO3 SDATA port bit 2, or GPIO2 SDATA port bit 1, or GPIO1 SDATA port bit 0, or GPIO0 +3.3 VDC Supply
7.0
SL11R CPU Programming Guide
This is the preliminary specification for the SL11R Processor Instruction set.
7.1
Instruction Set Overview
This document describes the SL11R CPU Instruction Set, Registers and Addressing modes, Instruction format, etc. The SL11R PROCESSOR uses a unified program and data memory space; although this RAM is also integrated into the SL11R core, provision has been made for external memory as well. The SL11R PROCESSOR engine incorporates 38 registers: fifteen general-purpose registers, a stack pointer, sixteen registers mapped into RAM, a program counter, and a REGBANK register whose function will be described in a subsequent section. The SL11R PROCESSOR engine supports byte and word addressing. Subsequent sections of this document will describe: * The SL11R PROCESSOR Engine (QT Engine) Register Set * SL11R PROCESSOR Engine Instruction Format * SL11R PROCESSOR Engine Addressing Modes * SL11R PROCESSOR Engine Instruction Set
7.2
Reset Vector On receiving hardware reset, the SL11R Processor jumps to address 0xFFF0, which is an internal ROM address.
Register Set
7.3
The SL11R Processor incorporates 16-bit general-purpose registers called R0..R15, a REGBANK register, and a program counter, along with various other registers. The function of each register is defined as follows: Name R0-R14 R15 PC REGBANK FLAGS INTERRUPT ENABLE General Purpose Registers Stack Pointer Program Counter Forms base address for registers R0-R15 Contains flags: defined below Bit masks to enable/disable various interrupts Function
7.4
General-Purpose Registers
The general-purpose registers can be used to store intermediate results, and to pass parameters to and return them from subroutine calls.
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7.5 General Purpose/Address Registers
In addition to acting as general-purpose registers, registers R8-R14 can also serve as pointer registers. Instructions can access RAM locations by referring to any of these registers. In normal operation, register R15 is reserved for use as a stack pointer.
7.6
REGBANK Register (0xC002: R/W)
Registers R0..R15 are mapped into RAM via the REGBANK register. The REGBANK register is loaded with a base address, of which the 11 most significant bits are used. A read from or write to one of the registers will generate a RAM address by: * Shifting the 4 least significant bits of the register number left by 1. * OR-ing the shifted bits of the register number with the upper 11 bits of the REGBANK register. * Forcing the Least Significant Bit to 0. For example, if the REGBANK register is left at its default value of 100 hex, a read of register R14 would read address 11C hex. Register REGBANK R14 RAM Location Note: Regardless of the value loaded into the REGBANK register, bits 0..4 will be ignored. Hex Value 0100 000E << 1 = 001C 011C Binary Value 00000001000xxxxx xxxxxxxxxx011100 0000000100011100
7.7
Flags Register (0xC000: Read Only)
The SL11R Processor uses these flags: FLAG bit: 15 0 Z C O S I Note: Flag behavior for each instruction will be described in the following section 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 I 3 S 2 O 1 C 0 Z
Zero: instruction execution resulted in a result of 0 Carry/Borrow: Arithmetic instruction resulted in a carry (for addition) or a borrow (for subtraction) Overflow: Arithmetic result was either larger than the destination operand size (for addition) or smaller than the destination operand should allow for subtraction Sign: Set if MS result bit is "1" Global Interrupts Enabled if "1"
7.8
Instruction Format
To understand addressing modes supported by the SL11R Processor, you must know how the instruction format is defined. In general, the instructions include four bits for the instruction opcode, six bits for the source operand, and six bits for the destination operand. ADD bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
opcode
source
destination
Some instructions, especially single operand-operator and program control instructions, will not adhere strictly to this format. They will be discussed in detail in turn.
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7.9
Addressing Modes
This section describes in detail the six-operand field bits referred to in the previous section as source and destination. Bear in mind that although the discussion refers to bits 0 through 5, the same bit definitions apply to the "source" operand field, bits 6 through 11. These are the basic addressing modes in the SL11R Processor. Mode Register Immediate Direct Indirect Indirect with Auto Increment Indirect with Index 54 00 01 3 r 1 210 r r r
111
1 0 b/w 1 1 1 0 1 b/w 1 0 b/w 1 1 b/w r r r r r r r r r
Notes: * b/w: `1' for byte-wide access, `0' for word access. * Indirect with auto increment and byte-wide Indirect addressing is illegal with the stack pointer (R15).
7.10
Register Addressing
In register addressing, any one of registers R0-R15 can be selected using bits 0-3. If register addressing is used, operands are always 16-bit operands, since all registers are 16-bit registers. For example, an instruction using register R7 as an operand would fill the operand field like this: Bits Register Operand 5 0 4 0 3 0 2 1 1 1 0 1
7.11
Immediate Addressing
In Immediate Addressing, the instruction word is immediately followed by the source operand. For example, The operand field would be filled with: Bits Operand field Note: In immediate addressing, the source operand must be 16 bits wide, eliminating the need for a b/w bit. 5 0 4 1 3 1 2 1 1 1 0 1
7.12
Direct Addressing
In Direct Addressing, the word following the instruction word is used as an address into RAM. Again, the operand can be either byte or word sized, depending on the state of bit 3 of the operand field. For example, to do a word-wide read from a direct address, the source operand field would be formed like this: Bits I/O operand Note: For a memory-to-memory move, the instruction word would be followed by two words, the first being the source address and the second being the destination. 5 1 4 0 3 0 2 1 1 1 0 1
7.13
Indirect Addressing
Indirect addressing is accomplished using address registers R8-15. In Indirect addressing, the operand is found at the memory address pointed to by the register. Since only eight address registers exist, only three bits are required to select an address register. For example, register R10 (binary 1010) can be selected by ignoring bit 3, leaving the bits 010. Bit 3 of the operand field
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is then used as the byte/word bit, set to "0" to select word or "1" to select byte addressing. In this example, a byte-wide operand is selected at the memory location pointed to by register R10: Bits Memory operand Note: For register R15, byte-wide operands are prohibited. If bit 3 is set high, the instruction is decoded differently, as explained at the top of this section. 5 0 4 1 3 1 2 0 1 1 0 0
7.14
Indirect Addressing with Auto Increment
Indirect Addressing with Auto Increment works identically to Indirect Addressing, except that at the end of the read or write cycle, the register is incremented by 1 or 2 (depending whether it is a byte-wide or word-wide access.) This mode is prohibited for register R15. If bits 0..2 are all high, the instruction is decoded differently, as explained at the top of this section.
7.15
Indirect Addressing with Offset
In Indirect Addressing with Offset, the instruction word is followed by a 16-bit word that is added to the contents of the address register to form the address for the operand. The offset is an unsigned 16-bit word, and will "wrap" to low memory addresses if the register and offset add up to a value greater than the size of the processor's address space.
7.16
Stack Pointer (R15) Special Handling
Register R15 is designated as the Stack Pointer, and has these special behaviors: * If addressed in indirect mode, the register pre-decrements on a write instruction, and post-increments on a read instruction, emulating Push and Pop instructions. * Byte-wide reads or writes are prohibited in indirect mode. * If R15 is addressed in Indirect with Index mode, it does not auto-increment or auto-decrement.
SL11R - CPU Instruction Set
The instruction set can be roughly divided into three classes of instructions: * Dual Operand Instructions (Instructions with two operands, a source and a destination) * Program Control Instructions (Jump, Call and Return) * Single Operand Instructions (Instructions with only one operand: a destination)
7.17
Dual Operand Instructions
Instructions with source and destination, for ALL dual operand instructions, byte values are zero extended by default. MOV bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0000 destination:= source Flags Affected: none ADD bit: 15 14 13 12 11 10
source
Destination
9
8
7
6
5
4
3
2
1
0
0001 destination:= destination + source Flags Affected: Z, C, O, S
source
Destination
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ADDC bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0010 destination:= destination + source + carry bit Flags Affected: Z, C, O, S SUB bit: 15 14 13 12 11 10
source
Destination
9
8
7
6
5
4
3
2
1
0
0011 destination:= destination - source Flags Affected: Z, C, O, S SUBB bit: 15 14 13 12 11 10
source
Destination
9
8
7
6
5
4
3
2
1
0
0100 destination:= destination - source - carry bit Flags Affected: Z, C, O, S CMP bit: 15 14 13 12 11 10
source
Destination
9
8
7
6
5
4
3
2
1
0
0101 [not saved] = destination - source Flags Affected: Z, C, O, S AND bit: 15 14 13 12 11 10
source
Destination
9
8
7
6
5
4
3
2
1
0
0110 destination:= destination & source Flags Affected: Z, S TEST bit: 15 14 13 12 11 10
source
Destination
9
8
7
6
5
4
3
2
1
0
0111 [not saved]:= destination & source Flags Affected: Z, S OR bit: 15 14 13 12 11 10
source
Destination
9
8
7
6
5
4
3
2
1
0
1000 destination:= destination | source Flags Affected: Z, S
source
Destination
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SL11R
XOR bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1001 destination:= destination ^ source Flags Affected: Z, S
source
Destination
7.18
Jcc bit:
Program Control Instructions
JUMP RELATIVE cccc 15 14 13 12 11 10 cccc 9 8 7 0 6 5 4 3 Offset 2 1 0
1100
PC:= PC + (offset*2)(offset is a 7-bit signed number from -64..+63) JccL bit: JUMP ABSOLUTE cccc 15 14 13 12 11 10 cccc 9 8 7 1 6 0 5 4 3 2 1 0
1100
Destination
PC:= [destination](destination is computed in the normal fashion for operand fields) Rcc bit: RET cccc 15 14 13 12 11 10 cccc 9 8 7 1 6 0 5 4 3 2 1 0
1100 PC:= [R15] R15++ Ccc CALL cccc bit: 15 14 13 12 11
010111
10 cccc
9
8
7 1
6 0
5
4
3
2
1
0
1010 R15-[R15]:= PC PC = [destination] INT bit: 15 14 13 12 11
Destination
10
9
8
7 0
6
5
4
3 int vector
2
1
0
1010 [R15]:= PC R15-PC = [int vector * 2]
0000
This instruction allows the programmer to implement software interrupts. Int vector is multiplied by two, and zero extended to 16 bits. Note: Interrupt vectors 0 through 31 may be reserved for hardware interrupts, depending on the application. The condition (cccc) bits for all of the above instructions are defined as:
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SL11R
Condition Z NZ C/B NC / AE S NS O NO A / NBE BE / NA G / NLE GE / NL L / NGE LE / NG (not used) Unconditional cccc Bits 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Unconditional JMP CALL RET Z=1 Z=0 C=1 C=0 S=1 S=0 O=1 O=0 (Z=0 AND C=0) (Z=1 OR C=1) (O= S AND Z=0) (O=S) (OS) (OS OR Z=1) Description JUMP mnemonic JZ JNZ JC JNC JS JNS JO JNO JA JBE JG JGE JL JLE CALL mnemonic CZ CNZ CC RNC CS CNS CO CNO CA CBE CG CGE CL CLE RET mnemonic RZ RNZ RC RNC RS RNS RO RNO RA RBE RG RGE RL RLE
Note: For the JUMP mnemonics, adding an "L" to the end indicates a long or absolute jump. Adding an "S" to the end indicates a short or relative jump. If nothing is added, the assembler will choose "S" or "L."
7.19
Single Operand Operation Instructions
Since Single operand instructions do not require a source field, the format of the Single operand Operation instructions is slightly different. Instruction bit: 15 14 13 12 11 10 9 8 1101*** 7 6543210 destination
[param]
Notice that the opcode field is expanded to seven bits wide. The four most significant bits for all instructions of this class are "1101." In addition, there is space for an optional three bit immediate value, which is used in a manner appropriate to the instruction. The destination field functions exactly as it does in the dual operand operation instructions. Note: * For the SHR, SHL, ROR, ROL, ADDI and SUBI instructions, the three-bit count or n operand is incremented by 1 before it is used. * The SL11R QT assembler takes this into account. SHR bit: 15 14 13 12 1101000 destination:= destination >> count Flags Affected: Z, C, S Note: * The SHR instruction shifts in sign bits. * The C flag is set with last bit shifted out of LSB. 11 10 9 8 7 count-1 6 5 4 3 2 1 0
destination
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SL11R
SHL bit: 15 14 13 12 1101001 destination:= destination << count Flags Affected: Z, C, S Note: The C flag is set with last bit shifted out of MSB. ROR bit: 15 14 13 12 1101010 11 10 9 8 7 count-1 6 5 4 3 2 1 0 11 10 9 8 7 count-1 6 5 4 3 2 1 0
destination
destination
Works identically to the SHR instruction, except that the LSB of destination is rotated into the MSB, as opposed to SHR, which discards that bit Flags Affected: Z, C, S ROL bit: 15 14 13 12 1101011 11 10 9 8 7 count-1 6 5 4 3 2 1 0
destination
Works identically to the SHL instruction, except that the MSB of destination is rotated into the LSB, as opposed to SHL, which discards that bit Flags Affected: Z, C, S ADDI bit: 15 14 13 12 11 10 9 8 7 n-1 6 5 4 3 2 1 0
1101100 destination:= destination + n Flags Affected: Z, S SUBI bit: 15 14 13 12 1101101 destination:= destination - n Flags Affected: Z, S NOT bit: 15 14 13 12 1101111 destination:= ~destination Flags Affected: Z, S NEG bit: 15 14 13 12 1101111 destination:= -destination Flags Affected: Z, O, C, S Document #: 38-08006 Rev. ** 11 10 9 8 11 10 9 8 11 10 9 8
destination
7 n-1
6
5
4
3
2
1
0
destination
7 000
6
5
4
3
2
1
0
destination
(bitwise 1's complement negation)
7 001
6
5
4
3
2
1
0
destination
(2's complement negation)
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SL11R
CBW bit: 15 14 13 12 1101111 Flags Affected: Z, S 11 10 9 8 7 010 6 5 4 3 2 1 0
destination
Sign-extends a byte in the lower eight bits of [destination] to a 16-bit signed word (integer).
7.20
STI bit:
Miscellaneous Instructions
15
14
13
12 1101111
11
10
9
8
7 111
6
5
4
3
2
1
0
000000
Sets interrupt enable flag Flags Affected: I Note: The STI instruction takes effect 1 cycle after it is executed. CLI bit: 15 14 13 12 11 10 9 8 111 7 6 5 4 3 2 1 0
1101111 Clears interrupt enable flag Flags Affected: I STC bit: 15 14 13 12 1101111 Set Carry bit. Flags Affected: C CLC bit: 15 14 13 12 1101111 Clear Carry bit. Flags Affected: C 11 10 9 11 10 9
000001
8
7 111
6
5
4
3
2
1
0
000010
8
7 111
6
5
4
3
2
1
0
000011
7.21
Built-in Macros
For the programmer's convenience, the SL11R QT assembler implements several built-in macros. The table below shows the macros, and the mnemonics for the code that the assembler will generate for these macros.
Macro INC X DEC X PUSH X POP X
Assembler will Generate ADDI X, 1 SUBI X, 1 MOV [R15], X MOV X, [R15]
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SL11R
7.22
SL11R Processor Instruction Set Summary
Opcode Flags Affected None Z,C,O,S Z,C,O,S Z,C,O,S Z,C,O,S Z,C,O,S Z,S Z,S Z,S Z,S None None None None None Z,C,S Z,C,S Z,C,S Z,C,S Z,S Z,S Z,S Z,O,C,S Z,S None None C C Clock Cycles 5 5 5 5 5 5 5 5 5 5 3 4 7 7 7 4 4 4 4 4 4 4 4 4 3 3 3 3
Mnemonic MOV ADD ADDC SUB SUBB CMP AND TEST OR XOR Jcc JccL Rcc Ccc Int SHR SHL ROR ROL ADDI SUBI NOT NEG CBW STI CLI STC CLC
Operands s,d s,d s,d s,d s,d s,d s,d s,d s,d s,d c,v c,d c c,d v n,d n,d n,d n,d n,d n,d d d d
Description Move s to d Add s to d Add s to d with carry Subtract s from d Subtract s from d with carry Compare d with s AND d with s Bit test d with s OR d with s XOR d with s Jump relative on condition 'c' Jump absolute on condition 'c' Return on condition 'c' Call subroutine on condition 'c' Software interrupt Shift right out of carry Shift left into carry Rotate right Rotate left Add immediate Subtract immediate 1's complement 2's complement Sign-extend d(7:0) to d(15:0) Enable interrupts Disable interrupts Set carry Clear carry
MSb 0000 ssss ssdd dddd 0001 ssss ssdd dddd 0010 ssss ssdd dddd 0011 ssss ssdd dddd 0100 ssss ssdd dddd 0101 ssss ssdd dddd 0110 ssss ssdd dddd 0111 ssss ssdd dddd 1000 ssss ssdd dddd 1001 ssss ssdd dddd 1100 cccc 0ooo oooo 1100 cccc 10dd dddd 1100 cccc 1001 0111 1010 cccc 10dd dddd 1010 0000 0vvv vvvv 1101 000n nndd dddd 1101 001n nndd dddd 1101 010n nndd dddd 1101 011n nndd dddd 1101 100n nndd dddd 1101 101n nndd dddd 1101 1110 00dd dddd 1101 1110 01dd dddd 1101 1110 10dd dddd 1101 1111 1100 0000 1101 1111 1100 0001 1101 1111 1100 0010 1101 1111 1100 0011
LSb
Notes 10,11 10,11 10,11 10,11 10,11 10,11 10,11 10,11 10,11 10,11 11 11 11 11 11 10,12,11 10,12,11 10,12,11 10,12,11 11 11 11 11 11 11 11 11 11
Notes: 10. The number in the "clock cycles" column reflects the number of clock cycles for register or immediate accesses. For each occurrence of other types of accesses, include the appropriate "clock adder" as listed in the Addressing Modes table below. 11. All clock cycle values assume zero wait-states. 12. A shift of one is done in four clock cycles, each additional shift adds two more clock cycles.
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SL11R
Opcode field descriptions Field S D C O V N Description Source Destination Condition code Signed offset Interrupt vector Count value -1 Addressing mode Register Immediate Direct Indirect Indirect with Auto Increment Indirect with Index 5 0 0 1 0 1 1 4 0 1 0 1 0 1 3 r 1 b/w b/w b/w b/w 2 r 1 1 r r r 1 r 1 1 r r r 0 r 1 1 r r r Clock Adder 0 0 1 1 2 3
b/w: '1' = byte access, '0' = word access. Indirect with auto-increment and byte-wide indirect addressing is illegal with R15.
8.0
8.1
SL11R - Electrical Specification
Absolute Maximum Ratings
This section lists the absolute maximum ratings of the SL11R. Stresses above those listed can cause permanent damage to the device. Exposure to maximum rated conditions for extended periods can affect device operation and reliability. Parameter Storage temperature Voltage on any pin with respect to ground Power Supply Voltage (VDD) Power Supply Voltage (VDD1) Lead Temperature (10 seconds) Junction Temperature (Tjmax) Range -40C to 125C -0.3V to 7.3V 3.3V10% 3.3V10% 180C 125C
8.2
Recommended Operating Conditions
Parameter Min. 3.0V 3.0V 0C Typical 3.3V Max. 3.6V 3.6V 65C
Power Supply Voltage, VDD Power Supply Voltage, VDD1 Operating Temperature
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SL11R
8.3 Crystal Requirements (XTAL1, XTAL2)
Crystal Requirements, (XTAL1, XTAL2) Operating Temperature Range Series Resonant Frequency Frequency Drift over Temperature Accuracy of Adjustment Series Resistance Shunt Capacitance Load Capacitance Driver Level Mode of Vibration 3rd overtone 20 W 3 pF 20 pF 5 mW
Min. 0C
Typical
Max. 65C
48 MHz 20 PPM 30 PPM 100 6 pF
8.4
External Clock Input Characteristics (XTAL1)
Parameter Min. 1.5V 48 MHz Typical Max.
Clock Input Voltage @ XTAL1 (XTAL2 is Opened) Clock Frequency
8.5
SL11R DC Characteristics
Parameter Description Input Voltage LOW Input Voltage HIGH Output Voltage LOW (IOL = 4 mA) Output Voltage HIGH (IOH = -4 mA) Output Current HIGH Output Current LOW Input Capacitance Supply Current (VDD) Supply Current (VDD1) Power dissipation Suspend Supply Current 2.4V 4 mA 4 mA 20 pF < 30 mA < 10 mA 0.7W < 220 A Min. -0.5V 2.0V Typical Max. 0.8V VDD + 0.3V 0.4V
VIL VIH VOL VOH IOH IOL CIN ICC IUSB Pd ICC +USB Susp.
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SL11R
8.6 SL11R USB Transceiver Characteristics
Parameter VIHYS VUSBIH VUSBIL VUSBOH VUSBOL ZUSBH[14] ZUSBL[14] Description Hysteresis On Input (Data+, Data-) USB Input Voltage HIGH USB Input Voltage LOW USB Output Voltage HIGH USB Output Voltage LOW Output Impedance HIGH STATE Output Impedance LOW STATE 28 28 0.8V 2.2V 0.7V 42 42 Min. 0.1V 1.5 V 1.3 V Typical[13] Max. 200 mV 2.0V
Notes: 13. All typical values are VDDx = 3.3 V and TAMB= 25C. 14. ZUSBX Impedance Values includes an external resistor of 28-42 1%
8.7
SL11R Reset Timing
treset
nRESET nRD or nWRL or nWRH tioact
Parameter treset tioact
Description nRESET Pulse width nRESET high to nRD or nWRx active
Min. 16 clocks 16 clocks
Typical
Max.
Note: Clock is 48 MHz nominal.
8.8
SL11R Clock Timing Specifications
tclk
X1
thigh
tlow
tfall
trise
Parameter tclk thigh tlow trise tfall
Description Clock period (48 MHz) Clock high time Clock low time Clock rise time Clock fall time Duty Cycle
Min. 20.0 ns 9 ns 9 ns
Typical 20.8 ns
Max.
11 ns 11 ns 5.0 ns 5.0 ns
-5%
+5%
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SL11R
8.9
8/16-bit DMA & DVC 8-bit DMA Mode: SDATA Port I/O Read Cycle (Non-DMA)
RCLK
t
APW
ADDR nCS t CPW
t nREAD t SD15-0
RPW
t
ACC
RDH
Data Valid
Parameter tAPW tCPW tRPW tACC tRDH
Description ADDR pulse width nCS pulse width Read pulse width Read access time Read high to data hold
Min. 30 ns 30 ns 30 ns
Typical
Max.
25 ns 10 ns
Note: RCLK is the resulting Clock (see Register 0xC006)
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SL11R
8.10 8/16-bit DMA & DVC 8-bit DMA Mode: SDATA Port I/O Write Cycle (Non-DMA)
RCLK t APW
ADDR t CWS nCS tWRPW nWRITE tDWS SD15-0 Data Valid t WDH t WCH
Parameter tAPW tCWS tWCH tWRPW tDWS tWDH
Description ADDR pulse width nCS low to write high set-up Write high to CS high hold Write pulse width Data setup to write high set-up Write high to data hold
Min. 20 ns 10 ns 5 ns 10 ns 10 ns 5 ns
Typical
Max.
Note: RCLK is the resulting Clock (see Register 0xC006)
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SL11R
8.11
8/16-bit DMA & DVC 8-bit DMA Mode: SDATA, DMA Read Cycle
DREQ nCS
DR
DCS
RDH
nREAD
D15-0
Data Valid
Parameter DCS DR RDH
Description DREQ high to CS low DREQ high to read low Read high to DREQ low hold
Min. 5 ns 5 ns
Typical
Max.
30 ns
8.12
8/16-bit DMA & DVC 8-bit DMA Mode: SDATA, DMA Write Cycle
DREQ nCS
DW
DCS
WDH
nWRITE
D15-0
Data Valid
Parameter DCS DWDH DW
Description DREQ high to CS low Write high to DREQ low hold DREQ high to write low
Min. 5 ns
Typical
Max.
30 ns 5 ns
8.13
SL11R Signals Name convention
SL11R Pin Name nRAS nCASH Data15-0 Data15-0 nXRAMSEL nWRL & nWRH Doc. Signal Name /WE (DRAM) /LCAS /OE Address /RD SL11R Pin Name nDRAMWR nCASL nDRAMOE A20-0 nRD /RAS /UCAS Dout Din /CS /WE (SRAM)
Doc. Signal Name
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SL11R
8.14 SL11R DRAM Timing
This timing is based on the SL11R Processor Clock (PCLK) = (2/3) of RCLK = 32MHz (see the register 0xC006 for information about PCLK). Parameter tRAS tCAS tRP tRCD tASR tRAH tASC tCAH tWCS tDS tDH tCRP tT tRPC tCSR tCPN tCHR tCAC tRAC tOAC tRC tOFF Description /RAS pulse width /CAS pulse width /RAS precharge time /RAS to /CAS delay time Row address set-up time Row address hold time Column address set-up time Column address hold time Write command set-up time Data set-up time Data hold time Delay time, /CAS pre-charge to /RAS Transition time (rise and fall) /RAS precharge to /CAS hold time /CAS set-up time /CAS precharge time /CAS hold time Access time from /CAS Access time from /RAS Access time from /OE Cycle time read Data out to High Z 80 ns 20 ns 150 ns 05 ns Min. 80 ns 20 ns 60 ns 64 ns 20 ns 36 ns 20 ns 36 ns 25 ns 05 ns 40 ns 05 ns 03 ns 00 ns 05 ns 10 ns 60 ns 20 ns Typical Max.
Note: This timing is base on EDO DRAM timing 16Mx16 devices. When the SL11R processor is set up for a higher speed (i.e. 48MHz clock), then the faster parts (i.e. 50ns or 60ns) should be used.
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SL11R
8.15
SL11R DRAM Read Cycle
tRC tRAS
RAS
tRP tRCD tCAS UCAS LCAS tASR tRAD tRAH tASC Row tCAH Column
Address
WE tCAC tRAC Dout tOAC Dout
OE
tOEP
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SL11R
8.16
SL11R DRAM Write Cycle
tRC tRAS
RAS
tRP tRSH tRCD tCSH tCAS tCRP
UCAS LCAS tASR tRAH tASC Row tCAH Column
Address
tWCS
tWCH
WE
tDS Din
tDH
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SL11R
8.17
SL11R CAS-Before-RAS Refresh Cycle
tRP nRAS tT tRPC tCPN
nCASL nCASH
tRAS
tRC
tRC tRP tRAS tRP
tRPC tCHR tCPN tCSR tCHR
tCSR
tCRP
A11-0
Data15-0
tOFF High-Z
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SL11R
8.18
SL11R DRAM Page Mode Read Cycle
tRC tRAS RAS tRP tCRP
tRCD UCAS LCAS tRAD tASR tRAH t t Column tRCHA t WE t Dout tRAC Din tDZC High-Z OE tDZO t tRCHR
t tCAS tCSH t
tCAL t tRCH t t t Dout tOFF2
tOH tOHR
tRDD
tOAC
tCDD
tCDD tWDD
tODD tOEP
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SL11R
8.19
DRAM Page Mode Write Cycle
tRC tRAS RAS tRSH tRCD UCAS LCAS tCSH tCAS tRP t
tRAH Address
tRAH
tASC tCAH Column
Row
tWCS WE tRAH Din
Dout
tWCH
tRAH
High-Z
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SL11R
8.20
SL11R SRAM Read Cycle
Address
CS tAR tCR RD tRPW tCDH tAC tRDH
Din
Data Valid
Parameter tCR tRDH tCDH tRPW[15] tAR tAC[16]
Description CS low to RD low RD high to data hold CS high to data hold RD low time RD low to address valid RAM access to data valid
Min. 1 ns 5 ns 3 ns 28 ns 1 ns
Typical
Max.
31 ns 3 ns 12 ns
Notes: 15. 0 wait state cycle. 16. tAC means at 0 wait states, with PCLK = 2/3 RCLK, the SRAM access time should be 12ns max. For a 1 wait state cycle, with PCLK = 2/3 RCLK, the SRAM access time should be at 12 + 31ns = 43ns max. See register 0xC006 description for PCLK information.
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SL11R
8.21
SL11R SRAM Write Cycle
Address tAW tCSW CS
tWC tWPW WE
tDW
tDH
Dout
Data Valid
Parameter tAW tCSW tDW tWPW tDH tWC
[17]
Description Write address valid to WE low CS low to WE low Data valid to WE high WE pulse width Data hold from WE high WE high to CS high
Min. 13 ns 13 ns 25 ns 28 ns 5 ns 15 ns
Typical
Max.
Note: 17. This is at 1 wait state with PCLK = 2/3 RCLK. For 2-wait states, add 31 ns.
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SL11R
8.22
2-Wire Serial Interface EEPROM Timing
1-EEPROM Bus Timing- Serial I/O
Tlow EECLK Tsu1 EEDATA IN Tsu2 EEDATA OUT Thold2 Thold1
Thigh
Tr
2-Start and Stop Definition EEDATA EEDATA EECLK EECLK START STOP
3- Data Validity
Data Change Data Stable
Note: Timing will conform to standard as illustrated in ATMEL AT24COX data sheet
Parameter Tlow Thigh Tr Tsu1 Thold1 Tsu2 Thold2 4.7 s min. 4.0 s min.
Min./Max. Timing
Notes See ATMEL Data Sheet for Complete Timing Detail
1.0 s max. 200 ns max. 0 ns 4.5 s min. 100 ns max.
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SL11R
8.23
Fast EPP Data/Address Read Cycle
RPW
nDTSRB nASTRB
RDS RDH
SD7-0
Data Valid
Parameter RPW RDS RDH
Description nDTSRB or nASTRB pulse width Data setup before nDTSRB or nASTRB high nDTSRB or nASTRB high to data hold
Min.
Typical 50 ns
Max.
5 ns 30 ns
8.24
Fast EPP Data/Address Write Cycle
WPW
nWRITE
WDA
nDTSRB nASTRB
RPW
DAW WDH
SD7-0
Data Valid
Parameter WPW RPW WDA DAW WDH
Description nWRITE pulse width nDTSRB or nASTRB pulse width nWRITE low to nDTSRB or nASTRB low nDTSRB or nASTRB high to nWRITE high nDTSRB or nASTRB high to data hold
Min.
Typical 85 ns 50 ns 10 ns 25 ns
Max.
30 ns
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SL11R
9.0
9.1
Package information
Drawings and Dimensions
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SL11R
9.2 Package Markings
SL11R-IDE YYWWSQFP-1.2 XXXX
YYWW = Date code XXXX = Product code
9.3
Thermal Specifications
Parameter Min. Typ. Max. 125C 65C/W 75C/W 0.8W
Junction Temperature (Tjmax) Package thermal impedance (ja) Dissipated power @ 65C ambient (Pmax)
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(c) Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
SL11R
10.0 Revision History
Document Title: SL11R USB Controller/16-Bit RISC Processor Data Sheet Document Number: 38-08006 REV. ** ECN NO. 110565 ISSUE DATE 12/14/01 ORIG. OF CHANGE BHA DESCRIPTION OF CHANGE Converted to Cypress Format from ScanLogic
Document #: 38-08006 Rev. **
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